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 Category: Special Topics: Thursday, September 09, 2010
 Special Topics

This section of SOCcentral.com puts the spotlight on areas of special interest to designers. All Special Topics features consist of SOCcentral Exclusive Feature Articles and Viewpoints, abstracts and links to relevant magazine and newspaper articles available online, and abstracts and links to whitepapers, conference papers, and application notes available online.


Most-Read SOCcentral Feature Articles
Seeing Is Believing: How Visualization Simplifies IC DRC
Verification Challenges Require Surgical Precision
Selecting an AES Solution
IC Floorplanning and Power Integrity
Defining a Universal Verification Methodology
Chip Power Model for Co-Design
Eliminating the "Long Loop" in FPGA Design
Low Power: The Next Big Challenge for FPGA Designers
DDR3 DRAM Takes Servers to Greener Pastures
Advanced Static Verification Is Indispensable

SOCcentral Feature Articles Archive

  SOCcentral Special Topics Features  
3D Integrated Circuits
Design for Manufacturing
Design for Test
ESL Design
Floorplanning & Layout
Formal Verification
Logic & Physical Synthesis
Low-Power Design
On-Chip Interconnect
Reconfigurable Computing
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL


2010-2011 Special Topics Calendar

MonthTopic DeadlineConferences
September• Circuit Simulation & Parasitic Extraction August 27SISPAD
October• Low-Power Design September 27 
November• Design for Test (DFT) October 28ITC
December• ESL Design November 26 
January • System Co-Design (Chip/Package/Board) December 26DesignCon
February • Verification Methodologies January 28DVCon, FPGA 2011
March • Design for Manufacture & Yield (DFM & DFY) February 25DATE, ISQED
April• Selecting & Integrating IPMarch 28 
May• Hardware/Software Co-Design April 27 ESC
June• FPGA Design Tools May 27DAC
Targeted Conference Dates:
SISPAD (Conference on Simulation of Semiconductor Processes and Devices), September 6-8, 2010
ITC (International Test Conference), November 2-4, 2010
DesignCon, January 31-February 3, 2011
FPGA 2011 (International Symposium on FPGAs), February 27-March 1, 2011
DVCon, February 28-March 3, 2011
DATE, March 14-18, 2011
ISQED, March 14-16, 2011
Embedded Systems Conference (ESC), May 2-5, 2011
DAC, June 5-10, 2011

All SOCcentral Special Topics features consist of a original technical articles, viewpoints, and sidebars; abstracts and links to relevant magazine and journal articles available online; and abstracts and links to white papers and application notes available online. (The only requirement for a white paper, app note, etc. to be included in a Special Topics feature is that it must be available without registration.) Exclusive articles and viewpoints contributed to a Special Topic are featured prominently on the SOCcentral.com home page, in addition to being featured on the relevant Special Topics "home page."

Contact Editor-in-Chief John Miklosz at 609-477-6308 if you would like to discuss a technical article/viewpoint/sidebar. You should also call or e-mail john_miklosz@soccentral.com with your suggestions for white papers, app notes, etc. to be included in the Special Topics feature; of if you need additional information or a copy of SOCcentral’s editorial guidelines.

Proposals for technical articles, viewpoints and sidebars should be submitted no later than the 1st of the month preceding the Special Topics feature, and all viewpoints and articles must be received no later than 5 working days preceding the feature month. The deadline for suggestions about the whitepapers, app notes, etc. that could be abstracted and included in a Special Topics feature is 3 days preceding the feature month.

Download an Adobe Acrobat (PDF) copy of SOCcentral's Guidelines for Viewpoints and Technical Articles which also contains the 2010-2011 Special Topics Calendar.

You might also be interested in reading GlobalSpec's whitepaper Technical Articles: A Tool for Effective Marketing which contains valuable information of targeting and writing technical articles.

Designer's Mall

SOCcentral Feature Articles

Seeing Is Believing: How Visualization Simplifies IC DRC (9/1/2010)

Verification Challenges Require Surgical Precision (8/16/2010)

Selecting an AES Solution (8/2/2010)

IC Floorplanning and Power Integrity (8/2/2010)

Defining a Universal Verification Methodology (7/23/2010)

Chip Power Model for Co-Design (7/12/2010)

Eliminating the "Long Loop" in FPGA Design (7/12/2010)

Low Power: The Next Big Challenge for FPGA Designers (7/12/2010)

DDR3 DRAM Takes Servers to Greener Pastures (7/1/2010)

Advanced Static Verification Is Indispensable (6/7/2010)

Controllable Automation and Interoperability Standards: Scaling Custom Digital Layout for Next-Generation Chip Design (6/7/2010)

Imagining Verification Success (6/2/2010)

The ROI of Hardware Configuration Management in IC Design Flows (6/1/2010)

Continuum (Analog) Analysis of Power Integrity (5/28/2010)

"Useful" Skew-Based Optimization (5/20/2010)

Evolving Your Organization’s ABV Capabilities (5/17/2010)

Design Reuse – It’s Time for New IP-Creation Tools (5/10/2010)

Low-Power Design Applications for Formal Verification (5/7/2010)

Enabling Assertion-Based Verification (5/7/2010)

Realizing ESL with Scalable Transaction-Level Models (5/3/2010)

A Look at Emulation vs. Simulation (4/22/2010)

The New Standard for 32-nm IC Physical Design and Signoff (3/11/2010)

A Look at ESL (3/11/2010)

An Overview of FPGA Market Dynamics (2/17/2010)

A Practical Approach to Adopting Formal Property Checking (2/10/2010)

An Easy Way to Adopt Statistical Timing Analysis and Do Better Designs (1/21/2010)

Harnessing the DSP Horsepower (1/18/2010)

Automating Advanced Clock-Gating Techniques During High-Level Synthesis (12/10/2009)

Bridging SOC Architectures for Faster Timing Closure (11/2/2009)

Accelerate Design Closure with Multi-Core Timing Analysis and Optimization (11/2/2009)

Probabilistic Timing Analysis (10/31/2009)

A Processor and DSP IP Selection Checklist (10/15/2009)

What, Why and How of Through-Silicon Vias (10/6/2009)

Test Standards Emerge to Improve 3D-Chip Yield (10/5/2009)

SoC System Management IP Virtualizes SOC System Management (10/2/2009)

DFM-Compliant IP: Why You Need It, How You Get It (9/9/2009)

Protocol Abstraction Views Simplify Chip Interconnect Debugging (9/7/2009)

The Key to Seamless and Rapid IP Integration (9/1/2009)

Staying On the Path to Moore’s Law Requires 3D Integration (8/19/2009)

Strategies for Managing Data Across Multi-Site Design Projects (8/5/2009)

Synthesis Needs to Change to Serve Modern Chip Design (8/3/2009)

New Flow for Automating Verification of ESD Design Rules (8/3/2009)

Analog and Mixed-Signal IC Debug (8/2/2009)

Emulation Finds Its Role (7/15/2009)

DAC in San Francisco: Hope to See You There! (7/8/2009)

Layout Automation for the Next Generation of Custom Chips (7/6/2009)

Reducing IC Power Consumption with Advanced Place-and-Route (6/22/2009)

Design and Verification Techniques for Clock Gating (5/21/2009)

Leveraging Standards When Times Are Tough (2/16/2009)

FPGA-to-ASIC Conversion (1/16/2009)

Casey at the Bat (12/16/2008)

Designing for State Retention (12/12/2008)

Challenges in 45-nm Physical Design (11/6/2008)

Deep Submicron Designs Challenge Physical Implementation Tools (11/6/2008)

Single, Unified Datamodel Key to Integrated IC Implementation Flow (11/6/2008)

Test Structures Make Designs Harder to Verify (10/28/2008)

Perfect Storm Brewing for Chip and Circuit Board Test (10/22/2008)

When Silicon Processes Shrink, Test Needs Expand (10/6/2008)

Maximizing Test Efficiency with BIST (10/5/2008)

Small Delay Defect Testing (10/5/2008)

Electrical Fuse Makes Repairable Memory Testing Easy (10/5/2008)

Comparing an IP-Centric DDR Solution with a System-Centric DDR Solution for Improved System Performance (9/8/2008)

Manufacturing Concerns Move Up the Design Cycle (9/2/2008)

Solving the DFM Interoperability Crisis (9/2/2008)

Systematic Yield Improvement Using BIST (9/2/2008)

The Shifting Landscape of DFM (9/2/2008)

A Comprehensive Approach to Manufacturing Variability (9/2/2008)

… But Will It Work? (9/2/2008)

What Ever Happened to Formal Verification? (8/5/2008)

What Hardware Designers Need to Know About Systemverilog Testbench Debug and Analysis (8/5/2008)

Combining Metrics from Simulation and Formal (8/5/2008)

Formal Verification Goes Mainstream (8/5/2008)

Meeting Serial Rapid IO Architectural Trends in 3.5G and 4G Base Stations (7/28/2008)

Art Imitating Life: Hardware Development Imitating Software Development (7/21/2008)

Multi-Corner, Multi-Mode Power Closure: The New Dimension in IC Design (6/9/2008)

Power Has Consequences, So Chill Out! (6/9/2008)

Automating Advanced Low-Power Multi-Voltage Design (6/9/2008)

Low Power Is Now a High Priority (6/9/2008)

Industry Leaders Define Next Priorities for Low Power (6/9/2008)

Beyond IR Drop: Dynamic Voltage Droops and Total Power Integrity (5/22/2008)

ESL Is Finally Ready for Prime Time (5/12/2008)

Standardization Opens Virtual Platforms to Mainstream Use (5/12/2008)

SystemVerilog Modeling Guidelines to Avoid Synthesis- Simulation Mismatches (4/28/2008)

DACeZine Index (4/22/2008)

A Power Integrity Wall Follows the Power Wall! (3/25/2008)

Customizable Processors (3/11/2008)

Faster Simulation and Enhanced Visibility Lead to Faster Verification Closure (2/8/2008)

Development of Embedded DSP Communications Algorithms for Software Defined Radio (1/23/2008)

Power Integrity and Energy-Aware Floorplanning (1/16/2008)

Parasitic Extraction Challenges for Designing Advanced Process ICs (1/9/2008)

Parasitics Move Model Order Reduction into Electronic Design Automation (1/3/2008)

Tame the Timing Margins in Your 65-nm Designs (1/3/2008)

Creating a Unified Power Flow (11/12/2007)

Applying Volume Diagnostics to Accelerate Yield Learning (11/5/2007)

ESL Synthesis Solution Improves Productivity for DSP Designs in ASICs and FPGA Devices (9/20/2007)

Silicon Validation via LFD Simulation (8/6/2007)

An Introduction to the VMM Register Abstraction Layer (7/30/2007)

Statistical Timing Analysis: Sign-off for a New Generation (7/19/2007)

Simultaneous Multi-Scenario Timing Optimization for High-Performance Digital IC Designs (7/12/2007)

Process Variations Require Integrated Sign-Off Solutions (7/6/2007)

Why High MHz Does Not Mean High Performance (5/31/2007)

Selecting the Optimum ASIC Technology for Your Design (5/1/2007)

Where Do Structured ASICs Fit? (5/1/2007)

Catapulting Fabless Start-Ups (4/24/2007)

Software-Centric Co-Design (4/20/2007)

Why We Need Standards for Transaction-Level Modeling (4/9/2007)

Practical Applications of Data Abstraction Techniques for Embedded Systems Debug (4/2/2007)

Using SystemC Reference Models in SystemVerilog Testbenches (4/2/2007)

System Integration and Testing Before First Hardware Availability? It's Possible! (3/1/2007)

Chip Designers Must Think Like Architects for Chip-Package Co-Design (2/26/2007)

SystemVerilog Assertions in an SOC Environment (2/2/2007)

Coding Guidelines for an Effective Methodology for SystemVerilog Assertions Local Variables (2/2/2007)

Error Checking and Functional Coverage with SystemVerilog Assertions (2/2/2007)

Reconfigurable Systems Craft a New Breed Of “Soft Appliances” that Deliver Topnotch Performance (1/8/2007)

Configurable Processors: The Next Evolutionary Step for Microprocessors (1/8/2007)

New Techniques for Testing Communications Devices (11/13/2006)

Synchronous Interconnect is Hitting the Wall (10/23/2006)

A Layered Approach to NoC (10/23/2006)

Making the Transition from Board Level Design to System-on-Chip (10/17/2006)

Why DRAM is Capturing Greater Designer Mind Share Today (9/25/2006)

Visibility Enhancement Technology for Late-Stage Verification (9/20/2006)

A Flexible Solution for Implementing Structured ASIC Designs (8/28/2006)

Evolution of Fuses in ICs: From Static Redundancy to Dynamic Speed Fixes (8/10/2006)

Building a Total Quality Experience into Silicon IP (8/10/2006)

DFM at DAC (7/14/2006)

SystemVerilog and SystemC: Two Standards Used Together to Design SOCs (7/14/2006)

The Love/Hate Relationship with DDR SDRAM Controllers (7/3/2006)

Transaction-level Debug in SystemVerilog Environment: the Best of Both Worlds (7/3/2006)

Avoiding Some Common Mistakes When Integrating USB IP Into Your SOC (7/3/2006)

Quality and Risk as a Selection Criteria for IP Using VSIA QIP 2.0 (7/3/2006)

Evaluate IP Timing Constraints Before Use in SOC Designs (7/1/2006)

Multicore This, Multiprocessor That: It’s all MPSoC (7/1/2006)

Using Dynamic and Static Power Rail Analysis to Maximize Results with Minimum Effort (6/26/2006)

What We Learned About Structured ASICs from RapidChip (6/16/2006)

Structuring a Solution (6/16/2006)

Video Technology Mixes with Structured ASICs (6/16/2006)

Structured ASICs and Platform FPGAs: Part 2 (6/16/2006)

The Structured ASIC Debate (6/16/2006)

Structured ASICs and Platform FPGAs (6/16/2006)

The Platform Strategy for CE Product Development (6/14/2006)

Seven Habits of Effective Formal Verification Planning (6/12/2006)

Combinational Equivalence Checking for Retimed Designs (6/12/2006)

Becoming the “Third Force” in FPGAs (6/9/2006)

Critical Area: A Metric for Yield Optimizations in Physical Design (6/5/2006)

Applying Transaction-Level Models for Design and Testbenches (6/5/2006)

Transactions for the Masses (5/22/2006)

Strategies to Prevent IC Failures in Volume Production (5/18/2006)

On-Chip Interconnects for Multi-Core Chips: A Software Perspective (5/8/2006)

Survey Shines Light on the State of ESL Design (5/8/2006)

Networks on Chip for Managing On-Chip Communications (5/8/2006)

Performance Is a Way to Differentiate (4/14/2006)

An EDA Veteran's Outlook from Sang Wang (4/14/2006)

Mixed-Abstraction Virtual System Prototypes Close SOC Design Gaps (4/14/2006)

Re-timing Verification Using Sequential Equivalence Checking (3/24/2006)

Transaction-Level Modeling and Advanced Verification Come Together with SystemC and SystemVerilog (3/24/2006)

Transaction-Level Modeling: SystemC and/or SystemVerilog (3/6/2006)

Using TLM to Speed Verification and Design (3/6/2006)

OVL Made Easy for Assertion-Based Verification (2/21/2006)

Deflecting the Design Diversity Dilemma: Methods for Improving Mixed-Signal Post-Layout Analysis in an SoC Flow (2/20/2006)

Your Power Grid Isn't Good Enough (2/20/2006)

System Level Design of FPGA-Based DSP Algorithms (12/19/2005)

Do’s and Don’ts of Architecting the Right FPGA Solution for DSP Design (12/15/2005)

FPGA-Centric Computing Architecture (12/15/2005)

Hard Macro Placement in Complex SoC Design (11/18/2005)

ESL: A Look at the Myths, the Legends and the Reality (11/18/2005)

Ensuring Serial Protocol Signal Integrity with FPGAs and Embedded Transceivers (11/17/2005)

Logic and Physical Synthesis: Should There Be a Difference? (11/15/2005)

FPGA Design Meets the Heisenberg Uncertainty Principle (11/5/2005)

The Evolution of FPGA Physical Synthesis (11/5/2005)

SoC Design Success: Winning with Standards (11/5/2005)

It’s All About the Routing, Stupid! (10/17/2005)

Graph-Based Physical Synthesis for FPGAs (10/17/2005)

Moore’s Law and the Need for a Revolution in Floorplanning Methodology (10/17/2005)

Technology Challenges Facing the Foundries (10/6/2005)

ASICs, ASSPs, and EMC in Automotive Systems Design (9/29/2005)

The Future of Configurable Microprocessing (9/7/2005)

Platform ASICs vs. FPGAs (9/1/2005)

Structured ASICs: A Risk Management Tool (9/1/2005)

FPGAs and Structured ASICs: A New Reality for ASSP Development (9/1/2005)

Standard-Metal: The Ultimate Structured ASIC Fabric (9/1/2005)

Top Five Reasons to Convert Your FPGA-to-ASIC (9/1/2005)

How Are You Planning to Verify all that DFT? (8/31/2005)

Testing an FPGA: When Is Enough, Enough? (8/22/2005)

IC-Catalyst: A Technology to Improve Silicon Engineering Productivity (8/8/2005)

Hybrid Optimization of High Performance Cell-Based Design (8/4/2005)

The VSIA and IP Reuse (8/2/2005)

Choosing a Structured/Platform ASIC: Understanding the Market Landscape (7/31/2005)

DFM: What Do the Letters Really Mean? (7/22/2005)

Networks on Chip: Challenges and Solutions (7/20/2005)

RTL Verification without Testbenches (7/11/2005)

Verilog-A/DoE: Simulating Behavioral Models Over Corners (7/7/2005)

EDA Tools Aim at Improving Yield (7/1/2005)

Improving Test Through Real-Time Information (7/1/2005)

Comprehensive Characterization Analysis Ensures Fast Yield Ramps (7/1/2005)

IP Quality is the Key to Successful SoC Design (6/6/2005)

Advanced Block-Level Bug-Hunting with Assertion-Based Verification Methodology and Hybrid Formal Verification (6/6/2005)

Can Formal Verification Techniques Save Design? (6/1/2005)

Communications Fabric Leverages Computing Power of FPGA Architectures (6/1/2005)

Boosting Processor Performance with an Optimized Coprocessor (6/1/2005)

Formal Verification with ABV Made Practical (6/1/2005)

System Verification for Reconfigurable Processor-Based Systems using SystemC (6/1/2005)

Configurable Processors: What, Why, How? (6/1/2005)

Software-Configurable Processors on the Rise (6/1/2005)

An EDA Giant's Take on Upcoming Challenges (5/31/2005)

Solving High-Speed Memory Interface Challenges with Low-Cost FPGAs (5/11/2005)

Structured ASIC Platforms with Integrated SerDes Cores Offer Performance at Low Cost (5/6/2005)

When Probing Goes in the Chip (5/2/2005)

The Next Five Years for FPGAs (5/1/2005)

Generating Faster-than-at-Speed Delay Tests with On Product Clock Generation (5/1/2005)

Why Haven't EDA Vendors Given Us DFT at the Register Transfer Level? (5/1/2005)

High Octane ATPG (5/1/2005)

Comparing ATPG Runs (5/1/2005)

The New DFT Reality at 90nm (5/1/2005)

Advancing Transaction Level Modeling: Linking the OSCI and OCP-IP Worlds at the Transaction Level (4/29/2005)

Evolution and Adoption of Formal Analysis (4/14/2005)

90-nm Custom SoC? Not That Hard When Most of It's Already Working (4/8/2005)

So What Use Are FPGAs -- Really? (4/4/2005)

Elements of Verification (3/25/2005)

Speeding Test Chip Creation and Revision Through Automation (3/18/2005)

On-Chip Power Integrity, Including Package Effects (3/11/2005)

Go with the Flow for Power Integrity (3/7/2005)

Placement-Driven Power Optimization at 90nm and Below (3/7/2005)

Synthesis from C in Electronic System Level (ESL) Design (2/16/2005)

Are You Building Your ESL Design Flow on Sand? (2/1/2005)

Communication Transactions Come First (2/1/2005)

MATLAB, the Next ESL for Embedded DSP Design (2/1/2005)

Complexity and Software Drive ESL Solutions (2/1/2005)

Design for Low-Power at the Electronic System Level (2/1/2005)

The Real Challenge of System-Level Design (2/1/2005)

Creating Power-Efficient Application Engines for SoC Designs (2/1/2005)

Rapid SoC Hardware/Software Co-Development Using Transaction Level Modeling (2/1/2005)

Speeding-up Signal Integrity Analysis and Repair for SoCs (1/3/2005)

An Alternative Approach to Circuit Design and Assembly for High Speed Interconnections (12/29/2004)

Can You Hear Me Now? (12/29/2004)

Components of a Complete Assertion-Based Verification Solution (12/13/2004)

Virtual Systems Prototyping Ensures Reusable Design Platforms (12/10/2004)

Accelerating SOC Design While Reducing Costs (10/25/2004)

Defining the Need for DSP Design Automation (6/18/2004)

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