SOCcentral Feature Articles |
Maximizing the Value of Your Internal IP, IPextreme, Inc. (5/15/2013) |
Yes, Virginia, There Is a Stitch-and-Ship, Breker Verification Systems, Inc. (4/5/2013) |
Formal Verification Works Well for Connectivity Checking, Mentor Graphics Corp. (3/15/2013) |
Verified Beyond Doubt, OneSpin Solutions GmbH (3/14/2013) |
Formal Verification and Validation, Gabe on EDA (3/14/2013) |
A Call to Action: How 20nm Will Change IC Design, Cadence Design Systems, Inc. (2/8/2013) |
Demystifying Analog and Mixed-Signal ASICs, JVD, Inc. (2/8/2013) |
Exposing the Hidden Costs of Using Off-the-Shelf Analog ICs, JVD, Inc. (1/14/2013) |
The SOC Interconnect-Verification Challenge, Test and Verification Solutions, Ltd. (TVS) (1/14/2013) |
TLM-Driven Design and Verification: Time for a Methodology Shift, Cadence Design Systems, Inc. (1/7/2013) |
Clock Domain Crossing Demystified, Real Intent, Inc. (1/3/2013) |
RTL Analysis for Complex FPGA Designs Using a Grey Cell Methodology, Blue Pearl Software, Inc. (1/2/2013) |
Changing the Paradigm of Electrical Test, GOEPEL electronic GmbH (1/2/2013) |
Power and Thermal Modeling and Analysis of Multi-Die Packages, DOCEA Power (12/17/2012) |
Building Energy-Efficient ICs from the Ground Up, Cadence Design Systems, Inc. (12/5/2012) |
The Case for Developing Custom Analog SOCs, S3 Group (12/3/2012) |
3D ICs with TSVs: Design Challenges and Requirements, Cadence Design Systems, Inc. (12/3/2012) |
Blindsided by a Glitch, Real Intent, Inc. (11/19/2012) |
Profiling Defect Sites for Yield Improvement, Mentor Graphics Corp. (11/9/2012) |
New IJTAG Standard Simplifies SOC Verification and Test Processes, ASSET InterTech, Inc. (11/5/2012) |
Solutions for Mixed-Signal SOC Implementation, Cadence Design Systems, Inc. (10/25/2012) |
Vendor-Independent RTL Memory BIST Insertion and Verification, Atrenta, Inc. (10/23/2012) |
The IP Blame Game, Methodics LLC (10/10/2012) |
Already Scanned Today?, GOEPEL electronic GmbH (9/21/2012) |
Use the Power of Your SOC to Verify Its Low-Power Design Features, Breker Verification Systems, Inc. (9/1/2012) |
Challenges and Requirements for Power-Aware Debugging, SpringSoft, Inc. (8/27/2012) |
SCE-MI Explained: Macro-based and Function-based, Aldec, Inc. (8/24/2012) |
Solutions for Mixed-Signal SOC Verification, Cadence Design Systems, Inc. (8/21/2012) |
Leapfrogging the Competition Through Smart IP Selection, CAST, Inc. (8/17/2012) |
Hybrid Prototyping Delivers the Best of Both Virtual and FPGA Prototyping to SOC Hardware and Software Teams, Synopsys, Inc. (8/3/2012) |
3D-IC System Verification Methodology: Solutions and Challenges, Mentor Graphics Corp. (7/20/2012) |
8051s in the Spectrum of Microcontroller Choices, CAST, Inc. (7/20/2012) |
Testing the 3D Waters, Mentor Graphics Corp. (7/19/2012) |
The Evolution of Power Format Standards, Cadence Design Systems, Inc. (7/16/2012) |
Understanding the Low Power Abstraction, Mentor Graphics Corp. (7/6/2012) |
New Tools Take the Pain out of FPGA Synthesis, Blue Pearl Software, Inc. (6/29/2012) |
Test Automation of 3D Integrated Systems, Synopsys, Inc. (6/29/2012) |
Power Is on Everybody's Mind, Emulation and Verification Engineering (EVE) (6/29/2012) |
The IP Distribution Challenge, Methodics LLC (6/15/2012) |
The Design and Verification Challenge for the Decade, Mentor Graphics Corp. (6/14/2012) |
Low-Power RTL Report 2012, Calypto Design Systems, Inc. (6/14/2012) |
Mixed-Signal Design Trends and Challenges, Cadence Design Systems, Inc. (6/1/2012) |
Driving A/MS Innovation: An EDA Ecosystem Approach, Tanner EDA (6/1/2012) |
Latest FPGAs Show Big Gains in Floating-Point Performance, HPCwire (5/16/2012) |
An Accurate DRAM Model, OCP International Partnership (OCP-IP) (5/14/2012) |
Augmenting the Transaction Generator with New DRAM and Workload Models, OCP International Partnership (OCP-IP) (5/11/2012) |
Reaching for the Cloud: What's Next for Interconnects, Sonics, Inc. (4/27/2012) |
Using Formal Technology to Improve Coverage Results, Mentor Graphics Corp. (4/23/2012) |
Resistive RAM: The Future Embedded Non-Volatile Memory?, Kilopass Technology, Inc. (4/9/2012) |
Hardware in the Software Sphere of Influence, Mentor Graphics Corp. (3/30/2012) |
Extending the Metric-Driven Verification Methodology to TLM, Cadence Design Systems, Inc. (3/30/2012) |
Streamlined Verification Plans Using the Metric Driven Verification Flow, Cadence Design Systems, Inc. (2/23/2012) |
Completing Hardware Innovation Cycles in Less than Six Months: An Internet Data Center Server Case Study, Synopsys, Inc. (2/1/2012) |
Understanding Formal Verification Concepts-Part 3, Atrenta, Inc. (1/31/2012) |
Understanding Formal Verification Concepts-Part 2, Atrenta, Inc. (1/16/2012) |
Simulation Coverage and Formal Verification: Unlikely Collaborators?, Synopsys, Inc. (1/13/2012) |
Understanding Formal Verification Concepts, Atrenta, Inc. (12/9/2011) |
Powering the Shift to HLS, Calypto Design Systems, Inc. (12/6/2011) |
Handling Clock Synchronization During Power-Driven Synthesis, Atrenta, Inc. (10/27/2011) |
Understanding the Cost of Not Prototyping, S2C, Inc. (10/24/2011) |
Breaking the Memory-Performance Bottleneck, Memoir Systems, Inc. (10/17/2011) |
A Verification Methodology for 3D-ICs, Mentor Graphics Corp. (10/3/2011) |
Improving At-Speed DFT Coverage Using Early RTL Testability Analysis, Avery Design Systems, Inc. (9/20/2011) |
Advanced Sign-Off…It's Trending!, Real Intent, Inc. (9/13/2011) |
FPGA Design: From Top-Down to Bottom-Up, Synopsys, Inc. (6/2/2011) |
Clarifying Language/Methodology Confusion in FPGA Design, Aldec, Inc. (6/1/2011) |
Adopting a Flexible FPGA Verification Methodology, SpringSoft, Inc. (6/1/2011) |
A Third Way in FPGA Development, Mentor Graphics Corp. (6/1/2011) |
Is Your CDC Tool of Sign-Off Quality?, Real Intent, Inc. (5/13/2011) |
Using Cost-Effective and Secure Field-Programmable 1T-OTP to Emulate MTP, Sidense Corp. (4/28/2011) |
Planning Formal Verification Closure, Mentor Graphics Corp. (4/20/2011) |
IP Gets Smarter, Sonics, Inc. (4/1/2011) |
Factors Compelling Greater Use of Embedded One-Time Programmable Memory, Kilopass Technology, Inc. (3/24/2011) |
Thru-Silicon Vias: Current State of the Technology, eSilicon Corp. (2/25/2011) |
Boost Verification Quality with Intelligent Testbench Automation, Mentor Graphics Corp. (2/23/2011) |
Mind the Design and Verification Gap, Real Intent, Inc. (2/16/2011) |
Using Formal Verification to Control X Propagation, Jasper Design Automation (1/19/2011) |
The Need for a Comprehensive SOC Test Platform, Mentor Graphics Corp. (1/16/2011) |
Do You Have the Next-Generation Verification Flow?, Satris Group, Ltd. (1/13/2011) |
Is CDC (Clock Domain Crossing) Analysis a Misnomer?, Real Intent, Inc. (1/10/2011) |
Deadly Reasons for Extraction Failure , Silicon Frontline Technology, Inc. (12/13/2010) |
Managing Open-Source Licensing for Semiconductors, Protecode, Inc. (11/19/2010) |
Seeing Is Believing: How Visualization Simplifies IC DRC, Mentor Graphics Corp. (9/1/2010) |
Verification Challenges Require Surgical Precision, Real Intent, Inc. (8/16/2010) |
Selecting an AES Solution, High Tech Marketing (8/2/2010) |
IC Floorplanning and Power Integrity, Anasim Corp. (8/2/2010) |
Defining a Universal Verification Methodology, Accellera (7/23/2010) |
Low Power: The Next Big Challenge for FPGA Designers, Mentor Graphics Corp. (7/12/2010) |
Chip Power Model for Co-Design, Apache Design Solutions, Inc. (7/12/2010) |
Eliminating the "Long Loop" in FPGA Design, GateRocket, Inc. (7/12/2010) |
DDR3 DRAM Takes Servers to Greener Pastures, Samsung Electronics Co. Ltd. (7/1/2010) |
Controllable Automation and Interoperability Standards: Scaling Custom Digital Layout for Next-Generation Chip Design, SpringSoft, Inc. (6/7/2010) |
Advanced Static Verification Is Indispensable, Mentor Graphics Corp. (6/7/2010) |
Imagining Verification Success, Real Intent, Inc. (6/2/2010) |
The ROI of Hardware Configuration Management in IC Design Flows, ClioSoft, Inc. (6/1/2010) |
Continuum (Analog) Analysis of Power Integrity, Anasim Corp. (5/28/2010) |
"Useful" Skew-Based Optimization, ATopTech, Inc. (5/20/2010) |
Evolving Your Organization’s ABV Capabilities, Mentor Graphics Corp. (5/17/2010) |
Design Reuse – It’s Time for New IP-Creation Tools, Cypress Semiconductor Corp. (5/10/2010) |
Enabling Assertion-Based Verification, Zocalo Tech, Inc. (5/7/2010) |
Low-Power Design Applications for Formal Verification, Jasper Design Automation (5/7/2010) |
Realizing ESL with Scalable Transaction-Level Models, Mentor Graphics Corp. (5/3/2010) |
A Look at Emulation vs. Simulation, Mentor Graphics Corp. (4/22/2010) |
The New Standard for 32-nm IC Physical Design and Signoff, Mentor Graphics Corp. (3/11/2010) |
A Look at ESL, SOCcentral (3/11/2010) |
An Overview of FPGA Market Dynamics, High Tech Marketing (2/17/2010) |
A Practical Approach to Adopting Formal Property Checking, Mentor Graphics Corp. (2/10/2010) |
An Easy Way to Adopt Statistical Timing Analysis and Do Better Designs, Extreme DA (1/21/2010) |
Harnessing the DSP Horsepower, Altera Corp. (1/18/2010) |
Automating Advanced Clock-Gating Techniques During High-Level Synthesis, Mentor Graphics Corp. (12/10/2009) |
Bridging SOC Architectures for Faster Timing Closure, ChipStart (11/2/2009) |
Accelerate Design Closure with Multi-Core Timing Analysis and Optimization, Mentor Graphics Corp. (11/2/2009) |
Probabilistic Timing Analysis, Library Technologies, Inc. (10/31/2009) |
A Processor and DSP IP Selection Checklist, Tensilica, Inc. (10/15/2009) |
What, Why and How of Through-Silicon Vias, Mentor Graphics Corp. (10/6/2009) |
Test Standards Emerge to Improve 3D-Chip Yield, ASSET InterTech, Inc. (10/5/2009) |
SoC System Management IP Virtualizes SOC System Management, ChipStart (10/2/2009) |
DFM-Compliant IP: Why You Need It, How You Get It, Mentor Graphics Corp. (9/9/2009) |
Protocol Abstraction Views Simplify Chip Interconnect Debugging, Mentor Graphics Corp. (9/7/2009) |
The Key to Seamless and Rapid IP Integration, Sonics, Inc. (9/1/2009) |
Staying On the Path to Moore’s Law Requires 3D Integration, Ziptronix, Inc. (8/19/2009) |
Strategies for Managing Data Across Multi-Site Design Projects, Integrated Device Technology, Inc. (IDT) (8/5/2009) |
Synthesis Needs to Change to Serve Modern Chip Design, New Tech Press (8/3/2009) |
New Flow for Automating Verification of ESD Design Rules, Mentor Graphics Corp. (8/3/2009) |
Analog and Mixed-Signal IC Debug, Dolphin Integration (8/2/2009) |
Emulation Finds Its Role, Emulation and Verification Engineering (EVE) (7/15/2009) |
Layout Automation for the Next Generation of Custom Chips, SpringSoft, Inc. (7/6/2009) |
Reducing IC Power Consumption with Advanced Place-and-Route , Mentor Graphics Corp. (6/22/2009) |
Design and Verification Techniques for Clock Gating, eInfochips, Ltd. (5/21/2009) |
Leveraging Standards When Times Are Tough, OCP International Partnership (OCP-IP) (2/16/2009) |
FPGA-to-ASIC Conversion, ViASIC, Inc. (1/16/2009) |
Casey at the Bat, (12/16/2008) |
Designing for State Retention, ARM (12/12/2008) |
Single, Unified Datamodel Key to Integrated IC Implementation Flow, Magma Design Automation, Inc. (11/6/2008) |
Challenges in 45-nm Physical Design, Mentor Graphics Corp. (11/6/2008) |
Deep Submicron Designs Challenge Physical Implementation Tools, SOCcentral (11/6/2008) |
Test Structures Make Designs Harder to Verify, Extreme DA (10/28/2008) |
Perfect Storm Brewing for Chip and Circuit Board Test, ASSET InterTech, Inc. (10/22/2008) |
When Silicon Processes Shrink, Test Needs Expand, SOCcentral (10/6/2008) |
Small Delay Defect Testing, Synopsys, Inc. (10/5/2008) |
Electrical Fuse Makes Repairable Memory Testing Easy, Mentor Graphics Corp. (10/5/2008) |
Comparing an IP-Centric DDR Solution with a System-Centric DDR Solution for Improved System Performance, Virage Logic Corp. (9/8/2008) |
Solving the DFM Interoperability Crisis, Silicon Integration Initiative, Inc. (Si2) (9/2/2008) |
The Shifting Landscape of DFM, Takumi Technology Corp. (9/2/2008) |
A Comprehensive Approach to Manufacturing Variability, Mentor Graphics Corp. (9/2/2008) |
… But Will It Work?, Sigrity, Inc. (9/2/2008) |
Manufacturing Concerns Move Up the Design Cycle, SOCcentral (9/2/2008) |
Combining Metrics from Simulation and Formal, Jasper Design Automation (8/5/2008) |
Formal Verification Goes Mainstream, SOCcentral (8/5/2008) |
What Ever Happened to Formal Verification?, Mentor Graphics Corp. (8/5/2008) |
What Hardware Designers Need to Know About Systemverilog Testbench Debug and Analysis, SpringSoft, Inc. (8/5/2008) |
Meeting Serial Rapid IO Architectural Trends in 3.5G and 4G Base Stations, Integrated Device Technology, Inc. (IDT) (7/28/2008) |
Art Imitating Life: Hardware Development Imitating Software Development, Mentor Graphics Corp. (7/21/2008) |
Power Has Consequences, So Chill Out!, Envis Corp. (6/9/2008) |
Low Power Is Now a High Priority, SOCcentral (6/9/2008) |
Multi-Corner, Multi-Mode Power Closure: The New Dimension in IC Design, Mentor Graphics Corp. (6/9/2008) |
Automating Advanced Low-Power Multi-Voltage Design, Synopsys, Inc. (6/9/2008) |
Industry Leaders Define Next Priorities for Low Power, Silicon Integration Initiative, Inc. (Si2) (6/9/2008) |
Beyond IR Drop: Dynamic Voltage Droops and Total Power Integrity, Anasim Corp. (5/22/2008) |
Standardization Opens Virtual Platforms to Mainstream Use, Synopsys, Inc. (5/12/2008) |
ESL Is Finally Ready for Prime Time, SOCcentral (5/12/2008) |
SystemVerilog Modeling Guidelines to Avoid Synthesis- Simulation Mismatches, Mentor Graphics Corp. (4/28/2008) |
A Power Integrity Wall Follows the Power Wall!, Anasim Corp. (3/25/2008) |
Customizable Processors, Tensilica, Inc. (3/11/2008) |
Development of Embedded DSP Communications Algorithms for Software Defined Radio , Agilent Technologies, Inc. (1/23/2008) |
Power Integrity and Energy-Aware Floorplanning, Anasim Corp. (1/16/2008) |
Parasitic Extraction Challenges for Designing Advanced Process ICs, Mentor Graphics Corp. (1/9/2008) |
Parasitics Move Model Order Reduction into Electronic Design Automation, EdXact (1/3/2008) |
Creating a Unified Power Flow, Mentor Graphics Corp. (11/12/2007) |
Applying Volume Diagnostics to Accelerate Yield Learning, Synopsys, Inc. (11/5/2007) |
Silicon Validation via LFD Simulation, Mentor Graphics Corp. (8/6/2007) |
An Introduction to the VMM Register Abstraction Layer, Synopsys, Inc. (7/30/2007) |
Statistical Timing Analysis: Sign-off for a New Generation, Extreme DA (7/19/2007) |
Simultaneous Multi-Scenario Timing Optimization for High-Performance Digital IC Designs, Athena Design Systems, Inc. (7/12/2007) |
Process Variations Require Integrated Sign-Off Solutions, Synopsys, Inc. (7/6/2007) |
Why High MHz Does Not Mean High Performance, Tensilica, Inc. (5/31/2007) |
Selecting the Optimum ASIC Technology for Your Design, ChipX Corp. (5/1/2007) |
Where Do Structured ASICs Fit?, AMI Semiconductor, Inc. (AMIS) (5/1/2007) |
Catapulting Fabless Start-Ups, Imagination Technologies, Ltd. (4/24/2007) |
Software-Centric Co-Design, CriticalBlue (4/20/2007) |
Why We Need Standards for Transaction-Level Modeling, GreenSocs (4/9/2007) |
Using SystemC Reference Models in SystemVerilog Testbenches, Synopsys, Inc. (4/2/2007) |
System Integration and Testing Before First Hardware Availability? It's Possible!, CoWare, Inc. (3/1/2007) |
Chip Designers Must Think Like Architects for Chip-Package Co-Design, Rio Design Automation, Inc. (2/26/2007) |
Error Checking and Functional Coverage with SystemVerilog Assertions, Cadence Design Systems, Inc. (2/2/2007) |
Coding Guidelines for an Effective Methodology for SystemVerilog Assertions Local Variables, Mentor Graphics Corp. (2/2/2007) |
Reconfigurable Systems Craft a New Breed Of “Soft Appliances” that Deliver Topnotch Performance, DRC Computer Corp. (1/8/2007) |
Configurable Processors: The Next Evolutionary Step for Microprocessors, Tensilica, Inc. (1/8/2007) |
New Techniques for Testing Communications Devices, Mentor Graphics Corp. (11/13/2006) |
Synchronous Interconnect is Hitting the Wall, Silistix, Ltd. (10/23/2006) |
A Layered Approach to NoC, Arteris SA (10/23/2006) |
Making the Transition from Board Level Design to System-on-Chip, Integrated Circuit Designs, Inc. (10/17/2006) |
Why DRAM is Capturing Greater Designer Mind Share Today, Samsung Electronics Co. Ltd. (9/25/2006) |
A Flexible Solution for Implementing Structured ASIC Designs, Magma Design Automation, Inc. (8/28/2006) |
Building a Total Quality Experience into Silicon IP, Synopsys, Inc. (8/10/2006) |
Evolution of Fuses in ICs: From Static Redundancy to Dynamic Speed Fixes, Cypress Semiconductor Corp. (8/10/2006) |
DFM at DAC, SOCcentral (7/14/2006) |
SystemVerilog and SystemC: Two Standards Used Together to Design SOCs, Accellera (7/14/2006) |
The Love/Hate Relationship with DDR SDRAM Controllers, MOSAID Technologies, Inc. (7/3/2006) |
Avoiding Some Common Mistakes When Integrating USB IP Into Your SOC, Mentor Graphics Corp. (7/3/2006) |
Quality and Risk as a Selection Criteria for IP Using VSIA QIP 2.0 , VSI Alliance (VSIA) (7/3/2006) |
Evaluate IP Timing Constraints Before Use in SOC Designs, Synopsys, Inc. (7/1/2006) |
Multicore This, Multiprocessor That: It’s all MPSoC, Tensilica, Inc. (7/1/2006) |
Using Dynamic and Static Power Rail Analysis to Maximize Results with Minimum Effort, Cadence Design Systems, Inc. (6/26/2006) |
Structuring a Solution, Triad Semiconductor, Inc. (6/16/2006) |
What We Learned About Structured ASICs from RapidChip, ViASIC, Inc. (6/16/2006) |
Structured ASICs and Platform FPGAs, SOCcentral (6/16/2006) |
The Structured ASIC Debate, AMI Semiconductor, Inc. (AMIS) (6/16/2006) |
Video Technology Mixes with Structured ASICs, Altera Corp. (6/16/2006) |
Structured ASICs and Platform FPGAs: Part 2, SOCcentral (6/16/2006) |
The Platform Strategy for CE Product Development, Altera Corp. (6/14/2006) |
Seven Habits of Effective Formal Verification Planning, Mentor Graphics Corp. (6/12/2006) |
Combinational Equivalence Checking for Retimed Designs, Synopsys, Inc. (6/12/2006) |
Becoming the “Third Force” in FPGAs, Lattice Semiconductor Corp. (6/9/2006) |
Critical Area: A Metric for Yield Optimizations in Physical Design, Synopsys, Inc. (6/5/2006) |
Applying Transaction-Level Models for Design and Testbenches, Mentor Graphics Corp. (6/5/2006) |
Transactions for the Masses, Mentor Graphics Corp. (5/22/2006) |
Strategies to Prevent IC Failures in Volume Production, eSilicon Corp. (5/18/2006) |
Networks on Chip for Managing On-Chip Communications, Arteris SA (5/8/2006) |
Survey Shines Light on the State of ESL Design, Mentor Graphics Corp. (5/8/2006) |
On-Chip Interconnects for Multi-Core Chips: A Software Perspective, PolyCore Software, Inc. (5/8/2006) |
An EDA Veteran's Outlook from Sang Wang, SOCcentral (4/14/2006) |
Mixed-Abstraction Virtual System Prototypes Close SOC Design Gaps, Carbon Design Systems, Inc. (4/14/2006) |
Performance Is a Way to Differentiate, Poseidon Design Systems, Inc. (4/14/2006) |
Transaction-Level Modeling and Advanced Verification Come Together with SystemC and SystemVerilog, Mentor Graphics Corp. (3/24/2006) |
Re-timing Verification Using Sequential Equivalence Checking, Calypto Design Systems, Inc. (3/24/2006) |
Transaction-Level Modeling: SystemC and/or SystemVerilog, Synopsys, Inc. (3/6/2006) |
Using TLM to Speed Verification and Design , Forte Design Systems, Inc. (3/6/2006) |
OVL Made Easy for Assertion-Based Verification, Mentor Graphics Corp. (2/21/2006) |
Deflecting the Design Diversity Dilemma: Methods for Improving Mixed-Signal Post-Layout Analysis in an SoC Flow, Mentor Graphics Corp. (2/20/2006) |
System Level Design of FPGA-Based DSP Algorithms, Poseidon Design Systems, Inc. (12/19/2005) |
Do’s and Don’ts of Architecting the Right FPGA Solution for DSP Design, Altera Corp. (12/15/2005) |
FPGA-Centric Computing Architecture, Nallatech, Ltd. (12/15/2005) |
ESL: A Look at the Myths, the Legends and the Reality, ARM (11/18/2005) |
Hard Macro Placement in Complex SoC Design, Synopsys, Inc. (11/18/2005) |
Ensuring Serial Protocol Signal Integrity with FPGAs and Embedded Transceivers, Altera Corp. (11/17/2005) |
Logic and Physical Synthesis: Should There Be a Difference?, Magma Design Automation, Inc. (11/15/2005) |
FPGA Design Meets the Heisenberg Uncertainty Principle, Mentor Graphics Corp. (11/5/2005) |
SoC Design Success: Winning with Standards, OCP International Partnership (OCP-IP) (11/5/2005) |
It’s All About the Routing, Stupid!, Pyxis Technology, Inc. (10/17/2005) |
Moore’s Law and the Need for a Revolution in Floorplanning Methodology, Magma Design Automation, Inc. (10/17/2005) |
Technology Challenges Facing the Foundries , SOCcentral (10/6/2005) |
ASICs, ASSPs, and EMC in Automotive Systems Design, AMI Semiconductor, Inc. (AMIS) (9/29/2005) |
The Future of Configurable Microprocessing, ARC International (9/7/2005) |
Standard-Metal: The Ultimate Structured ASIC Fabric, ViASIC, Inc. (9/1/2005) |
Platform ASICs vs. FPGAs , LSI Corp. (9/1/2005) |
FPGAs and Structured ASICs: A New Reality for ASSP Development , Altera Corp. (9/1/2005) |
Top Five Reasons to Convert Your FPGA-to-ASIC, AMI Semiconductor, Inc. (AMIS) (9/1/2005) |
Structured ASICs: A Risk Management Tool, eASIC Corp. (9/1/2005) |
How Are You Planning to Verify all that DFT?, Globetech Solutions (8/31/2005) |
Testing an FPGA: When Is Enough, Enough?, Xilinx, Inc. (8/22/2005) |
IC-Catalyst: A Technology to Improve Silicon Engineering Productivity, Open-Silicon, Inc. (8/8/2005) |
Hybrid Optimization of High Performance Cell-Based Design, Zenasis Technologies, Inc. (8/4/2005) |
The VSIA and IP Reuse, VSI Alliance (VSIA) (8/2/2005) |
Choosing a Structured/Platform ASIC: Understanding the Market Landscape, LSI Corp. (7/31/2005) |
DFM: What Do the Letters Really Mean?, Aprio Technologies, Inc. (7/22/2005) |
Networks on Chip: Challenges and Solutions, University of British Columbia (7/20/2005) |
RTL Verification without Testbenches, Calypto Design Systems, Inc. (7/11/2005) |
Verilog-A/DoE: Simulating Behavioral Models Over Corners, Cypress Semiconductor Corp. (7/7/2005) |
Improving Test Through Real-Time Information, Pintail Technologies, Inc. (7/1/2005) |
EDA Tools Aim at Improving Yield, Mentor Graphics Corp. (7/1/2005) |
Advanced Block-Level Bug-Hunting with Assertion-Based Verification Methodology and Hybrid Formal Verification, Synopsys, Inc. (6/6/2005) |
IP Quality is the Key to Successful SoC Design, VSI Alliance (VSIA) (6/6/2005) |
Software-Configurable Processors on the Rise, Stretch, Inc. (6/1/2005) |
Configurable Processors: What, Why, How?, Tensilica, Inc. (6/1/2005) |
System Verification for Reconfigurable Processor-Based Systems using SystemC, SoftJin Infotech Pvt. Ltd. (6/1/2005) |
Formal Verification with ABV Made Practical, Mentor Graphics Corp. (6/1/2005) |
Boosting Processor Performance with an Optimized Coprocessor, CriticalBlue (6/1/2005) |
Can Formal Verification Techniques Save Design?, Assertive Design, Inc. (6/1/2005) |
Communications Fabric Leverages Computing Power of FPGA Architectures, Nallatech, Ltd. (6/1/2005) |
An EDA Giant's Take on Upcoming Challenges, Synopsys, Inc. (5/31/2005) |
Solving High-Speed Memory Interface Challenges with Low-Cost FPGAs, Lattice Semiconductor Corp. (5/11/2005) |
Structured ASIC Platforms with Integrated SerDes Cores Offer Performance at Low Cost, Fujitsu Semiconductor America, Inc. (5/6/2005) |
When Probing Goes in the Chip, Agilent Technologies, Inc. (5/2/2005) |
The Next Five Years for FPGAs, Altera Corp. (5/1/2005) |
High Octane ATPG, Mentor Graphics Corp. (5/1/2005) |
Comparing ATPG Runs, Synopsys, Inc. (5/1/2005) |
Why Haven't EDA Vendors Given Us DFT at the Register Transfer Level?, DeFacTo Technologies (5/1/2005) |
Generating Faster-than-at-Speed Delay Tests with On Product Clock Generation, Cadence Design Systems, Inc. (5/1/2005) |
Advancing Transaction Level Modeling: Linking the OSCI and OCP-IP Worlds at the Transaction Level, Sonics, Inc. (4/29/2005) |
Evolution and Adoption of Formal Analysis, Cadence Design Systems, Inc. (4/14/2005) |
90-nm Custom SoC? Not That Hard When Most of It's Already Working, Toshiba America Electronic Components, Inc. (TAEC) (4/8/2005) |
So What Use Are FPGAs -- Really?, Altium, Ltd. (4/4/2005) |
Elements of Verification, eInfochips, Ltd. (3/25/2005) |
Speeding Test Chip Creation and Revision Through Automation, Stone Pillar Technologies, Inc. (3/18/2005) |
On-Chip Power Integrity, Including Package Effects, Sigrity, Inc. (3/11/2005) |
Placement-Driven Power Optimization at 90nm and Below , Synopsys, Inc. (3/7/2005) |
Synthesis from C in Electronic System Level (ESL) Design, Celoxica, Ltd. (2/16/2005) |
Complexity and Software Drive ESL Solutions, Synopsys, Inc. (2/1/2005) |
Are You Building Your ESL Design Flow on Sand?, Bluespec, Inc. (2/1/2005) |
Design for Low-Power at the Electronic System Level, ChipVision Design Systems AG (2/1/2005) |
The Real Challenge of System-Level Design, CoFluent Design (2/1/2005) |
Creating Power-Efficient Application Engines for SoC Designs, Synfora, Inc. (2/1/2005) |
Rapid SoC Hardware/Software Co-Development Using Transaction Level Modeling, CoWare, Inc. (2/1/2005) |
Speeding-up Signal Integrity Analysis and Repair for SoCs, Synopsys, Inc. (1/3/2005) |
An Alternative Approach to Circuit Design and Assembly for High-Speed Interconnections, SiliconPipe, Inc. (12/29/2004) |
Can You Hear Me Now?, Emulation and Verification Engineering (EVE) (12/29/2004) |
Components of a Complete Assertion-Based Verification Solution, Cadence Design Systems, Inc. (12/13/2004) |
Accelerating SOC Design While Reducing Costs, Synfora, Inc. (10/25/2004) |
Defining the Need for DSP Design Automation, Catalytic, Inc. (6/18/2004) |
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