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Category: Special Topics: Verilog:

Friday, September 03, 2010

Verilog

Featured Articles

Introduction to Verilog

This is a self-study course developed by Dr. John Sanguinetti for learning the Verilog Hardware Description Language. There are 9 chapters in the course. Each chapter has a number of topics and subsections which you visit by moving around in hypertext. The course is free, but you must first register.

The 9 chapters are: 1) Introduction, Hierarchy, and Modelling Structures; 2) Syntax, Lexical Conventions, Data Types, and Memories; 3) Expressions and Simulation Mechanics; 4) Gate Level Modeling; 5) Behavioral and Register Transfer Level Modeling; 6) Advanced Features; 7) Coding Style; 8) Debugging Verilog Models; 9) The Programming Language Interface.

View the course on the verilog.com website.

Aldec Evita Verilog Tutorial

Aldec has developed its Verilog Tutorial Tutorial to educate traditional schematic and mixed mode based users with the basic fundamentals for designing with the Verilog hardware description language. This Verilog centric tutorial will help ease the learning curve and include a series of questions and answers to test your knowledge at the end of each chapter.

The tutorial includes an interactive overview of the Verilog hardware description language as well as including a complete Verilog Reference Guide with over 150 topics providing definitions and examples of key Verilog terms and concepts.

Registration is required to download this tutorial. But well worth it.

View the tutorial on the Aldec, Inc. website.

Designer's Mall

SOCcentral news items about Verilog

WaveFormer Lite Generates Mixed-Signal HDL Test Benches for All FPGA Design Flows (8/11/2010)

Northwest Logic Verifies Compatibility of Its IP Cores with Aldec RTL Simulators (8/2/2010)

HDL Design House Announces HVT MX25L VITAL Behavioral Model (7/22/2010)

Hitachi Achieves 10,000X Performance Boost Using Cadence Technology to Verify Complex Design (7/19/2010)

Dolphin Integration Upgrades SLED and SMASH Tools (7/6/2010)

SynaptiCAD's VeriLogger Supports Encrypted Models from Actel, Altera, and Xilinx (7/1/2010)

Aldec Supports OVM and UVM in Riviera-PRO (6/21/2010)

Mentor Graphics Questa Functional Verification Platform Adopted by Mindtree (6/21/2010)

Paradigm Works Announces SystemVerilog FrameWorks Template Generator Support for UVM (6/11/2010)

Latest Release of Aldec's Riviera-PRO Supports OVM/UVM (6/8/2010)

Tiempo Unveils Timing-Driven Design Flow for Its Clockless Chip Design Technology (6/7/2010)

Mentor Graphics 0-In Formal Version 3.0 Brings New Level of Automation to Formal Verification (6/1/2010)

Altium Adds Aldec FPGA Simulation Technology to Altium Designer (5/25/2010)

Real Intent Improves Its Fast, Low-Noise Electronic Design Linter (5/13/2010)

Cadence Contributes Technology to Boost Verification of Complex Mixed-Signal Chips (4/21/2010)

Avery Design Systems Announces AMBA AXI and AHB Verification Solution (2/23/2010)

Paradigm Works Releases Free Open Source Software for VMM-based Verification (2/8/2010)

Cadence OVM SystemVerilog Solution Enables More Thorough Verification at Mitsubishi Electric (1/25/2010)

Real Intent Releases Ascent Lint Version 1.2 Offering New Rule Support with Low-Noise and High-Performance Linting (1/19/2010)

SynaptiCAD’s 64-Bit Verilog Simulator Now 30% Faster (1/18/2010)

Perfectus Announces Availability of SystemVerilog-Based OVM-Compliant PCI Express 3.0 Verification IP (1/6/2010)

Aldec Releases RTL Simulator with Enhanced Assertions and Xilinx SecureIP Support (12/24/2009)

Aldec Adds DO-254/ ED-80 Library to HDL Design Rule Checker (12/10/2009)

Maia EDA Launches New Automated Verification Tool (12/10/2009)

Aldec Announces Low-Cost Linux RTL and Gate-level Simulator (11/17/2009)

SynaptiCAD Offers a Free High-Performance Verilog 2001 Simulator (11/17/2009)

Gates-on-the-Fly Netlist Editor Adds Waveform Viewer Interoperability (11/4/2009)

Tiempo Chooses Verific Design Automation's SystemVerilog Front-End (10/29/2009)

EMA Partners with Aldec to Provide Cadence OrCAD Users a Complete FPGA Design Solution (10/16/2009)

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Magazine & Journal articles on Verilog

SystemVerilog Configurable Coverage Model In an OVM setup: Concept of Reusability EDA DesignLine (8/24/2010)

Generating AMD Microcode Stimuli Using VCS Constraint Solver Design & Reuse (7/29/2010)

Defining a Universal Verification Methodology SOCcentral (7/23/2010)

SystemVerilog-Based Generic Verification Methodology for IPs/ ASICs/ SOCs Design & Reuse (6/23/2010)

Enabling Assertion-Based Verification SOCcentral (5/7/2010)

Debugging and Analysis with SystemVerilog Testbench EDN Magazine (2/4/2010)

Using Formal for Design Space Exploration SCDsource (11/16/2009)

Using Tcl to Create a Virtual Component in Verilog Embedded Systems Design (embedded.com) (10/2/2009)

Protocol Abstraction Views Simplify Chip Interconnect Debugging SOCcentral (9/7/2009)

Tackling Formal Assumptions Through Verification Planning EDN Magazine (7/7/2009)

Using Advanced Logging Techniques to Debug and Test SystemVerilog HDL Code Embedded Systems Design (embedded.com) (5/12/2009)

Combining Yield and Performance in Behavioral Models for Analog ICs EDA Tech Forum (12/31/2008)

Building Reusable Verification Environments with OVM EDA Tech Forum (9/1/2008)

What Hardware Designers Need to Know About Systemverilog Testbench Debug and Analysis SOCcentral (8/5/2008)

Avoid FPGA Project Delays by Adopting Advanced Design Methodologies FPGA and Programmable Logic Journal (5/27/2008)

How to Raise the RTL Abstraction Level and Design Conciseness with SystemVerilog: Part 2 Programmable Logic DesignLine (5/14/2008)

How to Raise the RTL Abstraction Level and Design Conciseness with SystemVerilog: Part 1 Programmable Logic DesignLine (4/30/2008)

How to Implement SystemVerilog for FPGA Design FPGA and Programmable Logic Journal (4/29/2008)

Open Verification Methodology Allows Reusable Testbenches SCDsource (4/29/2008)

SystemVerilog Modeling Guidelines to Avoid Synthesis- Simulation Mismatches SOCcentral (4/28/2008)

Open Verification Methodology: Why Now? EDA DesignLine (4/1/2008)

Verify SOCs Faster and More Predictably with SystemVerilog and Constrained- Random Stimuli Electronic Design Magazine (3/5/2008)

VMM Application Packages: The Next Level of Productivity EDN Magazine (2/21/2008)

SystemVerilog is Coming to FPGA Design FPGA and Programmable Logic Journal (2/19/2008)

Practical Approaches to Deployment of SystemVerilog Assertions EDA DesignLine (4/3/2007)

Using SystemC Reference Models in SystemVerilog Testbenches SOCcentral (4/2/2007)

Coding Guidelines for an Effective Methodology for SystemVerilog Assertions Local Variables SOCcentral (2/2/2007)

Error Checking and Functional Coverage with SystemVerilog Assertions SOCcentral (2/2/2007)

SystemVerilog Assertions in an SOC Environment SOCcentral (2/2/2007)

SystemVerilog Reference Verification Methodology: VMM Adoption eeDesign (EE Times EDA News) (9/4/2006)

SystemVerilog and SystemC: Two Standards Used Together to Design SOCs SOCcentral (7/14/2006)

Transaction-level Debug in SystemVerilog Environment: the Best of Both Worlds SOCcentral (7/3/2006)

SystemVerilog Reference Verification Methodology: ESL eeDesign (EE Times EDA News) (6/12/2006)

A Bridging Model for ESL Synthesis eeDesign (EE Times EDA News) (5/29/2006)

SystemVerilog Gains a Foothold in Verification Electronic Design Magazine (5/25/2006)

SystemVerilog Reference Verification Methodology: RTL eeDesign (EE Times EDA News) (5/1/2006)

SystemVerilog Reference Verification Methodology: Introduction eeDesign (EE Times EDA News) (3/27/2006)

Transaction-Level Modeling and Advanced Verification Come Together with SystemC and SystemVerilog SOCcentral (3/24/2006)

Are You Designing with Too Many Significant Figures? FPGA and Programmable Logic Journal (3/21/2006)

Using SystemVerilog for Functional Verification eeDesign (EE Times EDA News) (12/5/2005)

How Verilog-AMS Accelerates Transistor Modeling eeDesign (EE Times EDA News) (8/1/2005)

Verilog-A/DoE: Simulating Behavioral Models Over Corners SOCcentral (7/7/2005)

A Tale of Two Languages: SystemC and SystemVerilog Chip Design Magazine (6/1/2005)

Getting to a Higher Level Electronic Design Magazine (3/31/2005)

Back to the Language Roots Embedded Systems Design (embedded.com) (12/20/2004)

Mixed HDLs plus HVL: Part 2, Using Specman Elite in a Mixed Verilog/VHDL Chip Verification Environment Chip Design Magazine (11/1/2004)

Mixed HDLs plus HVL: Part 1, Using Specman Elite in a Mixed Verilog/VHDL Chip Verification Environment Chip Design Magazine (9/1/2004)

How to Choose a Verification Methodology eeDesign (EE Times EDA News) (7/9/2004)

Synopsys "ARMs" SystemVerilog eeDesign (EE Times EDA News) (4/5/2004)

SystemVerilog Enhancements for All Chip Designers eeDesign (EE Times EDA News) (2/26/2004)

The Search for the Perfect Language EDN Magazine (2/5/2004)

How SystemVerilog Aids Design and Synthesis eeDesign (EE Times EDA News) (1/27/2004)

The C Programmers Guide to Verilog Embedded Systems Design (embedded.com) (7/9/2003)

An Overview of SystemVerilog 3.1 eeDesign (EE Times EDA News) (5/21/2003)

Toil and Trouble in ASIC Synthesis EDAVision (4/1/2002)

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Tutorials, White Papers and Conference Papers on Verilog

Advanced Stimulus Generation with DesignWare Verification IP and Verification Methodology Manual for SystemVerilog Synopsys, Inc.

Advanced Techniques for Building Robust Testbenches with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog Synopsys, Inc.

Automated Nonlinear Macromodeling of Output Buffers for High-Speed Digital Applications Design Automation Conference (DAC)

Automatic Abstraction and Verification of Verilog Models Design Automation Conference (DAC)

Automating Analog Verification in a Mixed-Mode Simulation asicNorth

Coding Techniques for Bus Functional Models In Verilog, VHDL, and C++ SynaptiCAD, Inc.

Correct Methods For Adding Delays To Verilog Behavioral Models Sunburst Design, Inc.

Delivering Synthesizable Verification IP for Test Benches Bluespec, Inc.

Designer's Guide to Verilog Doulos

Efficient Timing Closure Without Timing Driven Placement and Routing Design Automation Conference (DAC)

Evita Verilog Interactive Tutorial Aldec, Inc.

Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog Synopsys, Inc.

Free Models: What Are They? How Are They Used? How Can They Be Free? Free Model Foundry

Functional Verification of SiCortex Multiprocessor System-on-a-Chip (48.4) Design Automation Conference (DAC)

Introduction to Verilog verilog.com

It’s What The DAVEs In Your Company Asked For Sutherland HDL, Inc.

New Verilog-2001 Techniques for Creating Parmeterized Models Sunburst Design, Inc.

Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill! Sunburst Design, Inc.

PANEL: Building a Standard ESL Design and Verification Methodology: Is It Just a Dream? Design Automation Conference (DAC)

Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions Verilab, Ltd.

RTL Coding Styles That Yield Simulation and Synthesis Mismatches Sunburst Design, Inc.

Simulation and Synthesis Techniques for Asynchronous FIFO Design Sunburst Design, Inc.

Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons Sunburst Design, Inc.

State Machine Coding Styles for Synthesis Sunburst Design, Inc.

Synchronous Resets? Asynchronous Resets? Which One to Use? Sunburst Design, Inc.

Synthesizing SVA Local Variables for Formal Verification (5.3) Design Automation Conference (DAC)

SystemVerilog 2-State Simulation Performance and Verification Advantages Sunburst Design, Inc.

SystemVerilog 3.1a Language Reference Manual (LRM) Accellera

SystemVerilog Implicit Port Connections: Simulation and Synthesis Sunburst Design, Inc.

SystemVerilog Ports & Data Types For Simple, Efficient and Enhanced HDL Modeling Sunburst Design, Inc.

SystemVerilog Tutorial ASIC World

SystemVerilog Tutortial electrosofts.com

The Dangers of Living with an X (Bugs Hidden in Your Verilog) ARM

The Evil Twins of Verilog Synthesis Sunburst Design, Inc.

The Fundamentals of Efficient Synthesizable Finite State Machine Design using NC-Verilog and BuildGates Sunburst Design, Inc.

The Myth of SystemVerilog Interoperability Verilab, Ltd.

The Open Verification Methodology (OVM), OVM World

Using SystemVerilog Assertions for Functional Coverage Verilab, Ltd.

Using SystemVerilog Assertions in Gate-Level Verification Environments Verilab, Ltd.

Verilog Coding Styles For Improved Simulation Efficiency Sunburst Design, Inc.

Verilog HDL Quick Reference Guide Sutherland HDL, Inc.

Verilog Nonblocking Assignments With Delays, Myths & Mysteries Sunburst Design, Inc.

Verilog Tutorial Yankee Bush Software

Verilog Tutorial University of Maryland (ECE)

Verilog-2001 Behavioral and Synthesis Enhancements Sunburst Design, Inc.

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