Category: Special Topics: Signal Integrity:

Thursday, September 09, 2010

Signal Integrity

An Alternative Approach to Circuit Design and Assembly for High Speed Interconnections

Current traditional approaches to PCB design and manufacture meet up with numerous signal integrity problems at high data rates. Manufacturing artifacts such as inconsistencies in dielectric properties, inconsistencies in trace width, variation in circuit spacing, uneven copper thickness and/or adhesion treatments can impact signal performance. In addition, the standard electrical concerns of resistance, dielectric loss, conductor loss, stray capacitance elements, signal skew and inductance/cross talk and potential reflections due to electronic stubs from circuit features such as vias, also appear at high data rates. The net of this complex problem set is that they make it extremely difficult to predict and design for maximum performance.

This article describes a new approach which segregates the high speed signals from all lower speed signals and power and ground connections. In practice, high speed signal sources are interconnected with controlled impedance links that are fabricated separately from the PCB and later interconnected directly between IC packages where required. Thus, instead of trying to precisely control a complex printed circuit design into a monolithic interconnect, the signals are instead segregated and critical signals are shepherded to a more easily controlled interconnection paths that lead directly from chip-to-chip or chip to other suitable electronic device.

Read the entire SiliconPipe, Inc. article on SOCcentral.

Basic Principles of Signal Integrity

Digital designs have not traditionally suffered by issues associated with transmission line effects. At lower frequencies the signals remain within data characterization and the system performs as designed. But as system speeds increase, the higher frequency impact on the system means that not only the digital properties, but also the analog effects within the system must be considered. These problems are likely to come to the forefront with increasing data rates for both I/O interfaces and memory interfaces, but particulalry with the high-speed transciever technology being embedded into FPGAs.

Transmission line effects can have a significant effect on the data being sent. At low speeds, the frequency response has little influence on the signal, unless the transmission medium is particularly long. However, as speed increases, high-frequency effects take over and even the shortest lines can suffer from problems such as ringing, crosstalk, reflections, and ground bounce, seriously hampering the integrity (response) of the signal. You can overcome these issues by following good design techniques and simple layout guidelines, as described in this document.

Read the entire article on the Altera Corp. website.

Signal Integrity Modeling and Simulation Tools

The ability to accurately model and simulate signal integrity is of utmost importance in high-speed electronic designs. While there exist tools for 3D parasitic extraction and ground bounce analysis in complex geometries, we also need many design aids to develop design rules and correlate simulation results with measurements. In this paper, we discuss some of these essential tools and the theories behind them.

Read the entire article on the Optimal Corp. website.

Speeding-up Signal Integrity Analysis and Repair for SoCs

The last thing you want after detailed routing is to spend a lot of time finding and fixing signal integrity (SI) problems. You can minimize SI issues with good prevention techniques in design planning, but you also need an efficient back-end sub-flow for detecting and fixing the problems. As part of this sub-flow, you need the ability to perform incremental what-if modeling of fixes in static timing analysis (STA) to take advantage of an STA tool's fast run times. Sometimes you can also save time by making fixes manually.

These techniques can help minimize the number of iterations through the SI analysis/repair sub-flow. No matter how well integrated these steps are, the full sub-flow is required to ensure that SI problems are fixed. However, incremental what-if modeling of fixes (whether automatic or manual) in STA can save a great deal of time by showing that a fix will probably work. This article focuses on such analysis and repair techniques that help shorten this critical process.

Read the entire Synopsys, Inc. article on SOCcentral.

Designer's Mall

SOCcentral news items about Signal Integrity

TSMC Selects Sigrity as a Reference Flow 11.0 Partner (6/29/2010)

Mentor Graphics' Olympus-SoC Place-and-Route System Now Supported By X-FAB (6/17/2010)

Apache Design Solution's Power and Noise Products Adopted by MoSys for IP Validation and Sign-Off (5/20/2010)

STMicroelectronics' Adopts Magwel's Full-Wave 3D Product for Advanced Signal-Integrity Analysis and Visualization (4/28/2010)

TSMC Expands Cadence Tool Support In Integrated Sign-Off Flow By Adding Synthesis, Place and Route, and RC Extraction (4/14/2010)

ANSYS Releases Ansoft Designer with Nexxim 5.0 Software (12/3/2009)

Vitesse Adds to Family of 11.5-Gbps Crosspoint Switches (9/28/2009)

Mindspeed Technologies Introduces a Low-Power Signal Integrity Solution for Broadcast Video Applications (9/14/2009)

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Magazine & Journal articles on Signal Integrity

IC Floorplanning and Power Integrity SOCcentral (8/2/2010)

Continuous-Time Equalizers Improve High-Speed Serial Links EDN Magazine (4/8/2010)

Swimming In the Channel EDN Magazine (3/18/2010)

Tools Accurately Simulate Noise in Mixed-Signal ASICs EDN Magazine (2/4/2010)

Preamplifier and Read-Channel Design Addresses Hard-Drive Goals EDN Magazine (12/3/2009)

Meeting USB 3.0 Performance and Ease-of-Use Expectations Electronic Products (12/1/2009)

Blocking Out the Noise Means Selecting the Right Filter Electronic Design Magazine (8/27/2009)

Reducing System Noise with Hardware Techniques EDA Tech Forum (7/15/2009)

Defeat Ground Bounce, Far End and Near End Cross Talk EDA Tech Forum (4/1/2009)

Power-Rail Filtering Improves PLL Performance EDN Magazine (3/19/2009)

Designing Protective Circuitry for DSL loops: Beware of Pitfalls EDN Magazine (12/5/2008)

The New Wave in High-Speed Modeling Printed Circuit Design & Fab (10/1/2008)

Spread Spectrum Clock generators Reduce EMI and Signal Integrity Problems EDN Magazine (7/24/2008)

Multi-Corner Multi-Mode Signal Integrity Optimization EDA Tech Forum (6/1/2008)

Overcoming USB Measurement Test-Setup Issues EDN Magazine (5/13/2008)

Solve Design Problems with Signal Integrity Optimization Printed Circuit Design & Fab (4/1/2008)

Fast Transient Noise Analysis for PLLs and ADCs SCDsource (3/19/2008)

RFI: Keeping Noise Out of Your Designs EDN Magazine (1/10/2008)

Avoiding Noise and EMI Problems in DSP Systems DSP DesignLine (1/7/2008)

Quantify FPGA System-Level Simultaneous Switching Noise in a Chip/ Package/ PCB Design Embedded Systems Design (embedded.com) (12/21/2007)

How to Enhance Signal Integrity in High-Density FPGA-based Designs Embedded Systems Design (embedded.com) (9/13/2007)

TDR: Taking the Pulse of Signal Integrity EDN Magazine (9/3/2007)

FPGA Packaging and Signal Integrity: A Connectivity Perspective FPGA and Programmable Logic Journal (5/29/2007)

Signal Integrity Analysis in Wireless SoCs EDA DesignLine (5/14/2007)

How to Test the Interconnections Between FPGAs on a High-Density FPGA-based Board Programmable Logic DesignLine (4/11/2007)

Designing PC Boards with Speedy FPGAs Embedded Systems Design (embedded.com) (4/9/2007)

Signal Integrity Approaches Meet the Multi-Gbps Design Challenge PlanetAnalog (3/25/2007)

How to Use Composite Current Source Modeling for Crosstalk Noise Analysis Embedded Systems Design (embedded.com) (3/9/2007)

Weapons of Noise Detection Electronic Design Magazine (2/1/2007)

How to Design 65-nm FPGA DDR2 Memory Interfaces for Signal Integrity Programmable Logic DesignLine (1/24/2007)

Quickly Find Elusive Signal-Integrity Problems in High-Speed Designs Electronic Design Magazine (12/15/2006)

Handling Differential Skew in High-Speed Serial Buses EDN Magazine (10/26/2006)

Maintaining Channel Compliance in High-Speed Backplanes EDN Magazine (10/12/2006)

Circulating Currents: The Warnings Are Out EDN Magazine (9/28/2006)

Is Chip Design Different After 90nm? EDN Magazine (7/6/2006)

On-Chip Variation and Timing Closure EDN Magazine (6/22/2006)

Easing the Modeling of Lossy Lines EDN Magazine (4/13/2006)

Dealing with PLL Clock Jitter in Advanced Processor Designs: Part 2 Embedded Systems Design (embedded.com) (3/8/2006)

Dealing with PLL Clock Jitter in Advanced Processor Designs: Part 1 Embedded Systems Design (embedded.com) (2/27/2006)

Signal Conditioning for High-Impedance Sensors EDN Magazine (2/16/2006)

Meeting Signal Integrity Requirements in FPGAs with High-End Memory Interfaces Programmable Logic DesignLine (1/18/2006)

High-Speed PCB Design: Symmetry and Spinoffs eeDesign (EE Times EDA News) (1/2/2006)

Ensuring Serial Protocol Signal Integrity with FPGAs and Embedded Transceivers SOCcentral (11/17/2005)

Board Decoupling Using a Standard Methodology EDN Magazine (10/27/2005)

IBIS 4.1 Enhances Signal Integrity Modeling eeDesign (EE Times EDA News) (7/4/2005)

Selecting the FPGA that Meets Your Signal Integrity Requirements FPGA and Programmable Logic Journal (5/17/2005)

How FPGA Packaging Drives Signal Integrity eeDesign (EE Times EDA News) (5/16/2005)

Reliable Sign-off at Smaller Nodes EDN Magazine (5/12/2005)

Modeling Gigabit Backplanes from Measurements EDN Magazine (3/17/2005)

Getting to Silicon: Accuracy Requirements of Nanometer Designs EDN Magazine (2/17/2005)

Techniques for Reducing Signal-Integrity Pessimism eeDesign (EE Times EDA News) (1/24/2005)

Speeding-up Signal Integrity Analysis and Repair for SoCs SOCcentral (1/3/2005)

High-Speed Chips Advance Signal Integrity Electronic Engineering Times (EE Times) (12/20/2004)

Control High-Frequency Effects When Distributing Power To DSPs Electronic Design Magazine (8/23/2004)

Cu Links on the Straight and Narrow Electronic Engineering Times (EE Times) (8/9/2004)

Modeling and Design Techniques Reduce 90nm Power eeDesign (EE Times EDA News) (8/6/2004)

Analysis of Board Layout Helps Cure Jitter Problems EDN Magazine (8/5/2004)

Power Integrity Requires Global I/O SSO Analysis eeDesign (EE Times EDA News) (6/16/2004)

A Matter of Integrity: SI Issues Hit FPGAs on Board FPGA and Programmable Logic Journal (4/27/2004)

A New Approach to Nanometer Delay Modeling eeDesign (EE Times EDA News) (3/4/2004)

What You Lose from a Lossy Line EDN Magazine (2/19/2004)

Reshaping the SoC Power Design Flow eeDesign (EE Times EDA News) (2/6/2004)

Speedy Processor Runs on Low Power Electronic Engineering Times (EE Times) (1/22/2004)

Noise 101 EDN Magazine (1/8/2004)

Achieving Signal Integrity for ASICs, PCBs and Packages eeDesign (EE Times EDA News) (12/19/2003)

Signal Integrity Key for Gbit Interconnects Electronic Engineering Times (EE Times) (12/8/2003)

Unified Data Model Brings Signal Integrity Electronic Engineering Times (EE Times) (12/8/2003)

Designing Controlled-Impedance Vias EDN Magazine (10/2/2003)

Packaging Concern: Signal Integrity Issues Rise with 500 Mbit/sec Rates Electronic Engineering Times (EE Times) (5/23/2003)

Crosstalk Glitch Analysis: How to Get it Right eeDesign (EE Times EDA News) (1/17/2003)

Engineer's "Rule of Thumb" Simplifies PCB Signal Integrity eeDesign (EE Times EDA News) (8/19/2002)

I/O Buffer Timing Ensures Board Signal Integrity Electronic Engineering Times (EE Times) (7/9/2002)

VSIA Guidelines Assist SoC Signal Integrity eeDesign (EE Times EDA News) (7/9/2002)

IC Layout Must Avoid Crosstalk Problems Electronic Engineering Times (EE Times) (6/5/2002)

Signal Integrity Drives Post-layout Verification eeDesign (EE Times EDA News) (6/5/2002)

Signal Integrity Permeates Design Process eeDesign (EE Times EDA News) (6/5/2002)

Static Crosstalk Analysis Assures Silicon Success eeDesign (EE Times EDA News) (6/5/2002)

Signal Integrity Methodology on 300 MHz SoC Design Using ALF Libraries and Tools EDAVision (5/1/2002)

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Tutorials, White Papers and Conference Papers on Signal Integrity

A CPPLL Hierarchical Optimization Methodology Considering Jitter, Power and Locking Time Design Automation Conference (DAC)

A Design Methodology for the I/O Power Supply of Next Generation Packaging Sigrity, Inc.

A Multi-Port Current Source Model for Multiple Input Switching Effects in CMOS Library Cells Design Automation Conference (DAC)

A New Twisted Differential Line Structure in Global Bus Design (10.4) Design Automation Conference (DAC)

A Noise-Driven Effective Capacitance Method With Fast Embedded Noise Rule Calculation for Functional Noise Analysis Design Automation Conference (DAC)

A Novel Technique to Improve Noise Immunity of CMOS Dynamic Logic Circuits Design Automation Conference (DAC)

A Scalable Soft Spot Analysis Methodology for Compound Noise Effects in Nano-Meter Circuits Design Automation Conference (DAC)

A Simulation Study of Simultaneous Switching Noise Sigrity, Inc.

A Unified Approach of PM Noise Cancellation in Large RF Multitone Autonomous Circuits Mentor Graphics Corp.

Achieving 3.2 Gb/s, 400 MTS AGTL+ IO Through Robust Power DeliveryDesign with Minimal Package Size Sigrity, Inc.

Basic Principles of Signal Integrity Altera Corp.

Beyond DDR: Signal Integrity and Timing Analysis of Quad Band Memory (QBM) Systems Signal Integrity Software, Inc. (SiSoft)

Closed-Form Expressions of Distributed RLC Interconnects for Analysis of On-Chip Inductance Effects Design Automation Conference (DAC)

Closing the Nanometer Yield Chasm Cadence Design Systems, Inc.

Computationally Efficient Power Integrity Simulation for System-on-Package Applications (34.2) Design Automation Conference (DAC)

Constraint-Aware Robustness Insertion for Optimal Noise-Tolerance Enhancement in Digital VLSI Circuits Design Automation Conference (DAC)

Design Integrity Issues Affecting Mixed-Signal Designs Mentor Graphics Corp.

Design Techniques for High-speed Source Synchronous Buses Signal Integrity Software, Inc. (SiSoft)

Distributed Models for Multi-Terminal Capacitors – Using 2D Lossy Transmission-Line Approach Sigrity, Inc.

Effective Decoupling Radius of Decoupling Capacitor Sigrity, Inc.

Effects of 20-H Rule and Shielding Vias on Electromagnetic Radiation from Printed Circuit Boards Sigrity, Inc.

Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew (10.5) Design Automation Conference (DAC)

Effects of Power and Ground Via Distribution on the Power and Ground Performance of C4/BGA Packages Sigrity, Inc.

Efficient Signal and Power Integrity Analysis Using Parallel Techniques Sigrity, Inc.

EMI Reduction and PCB Layout Techniques TLSI, Inc.

Experimental Jitter Analysis in a FlexCAN Based Drive-by-Wire Automotive Application (16.3) Design Automation Conference (DAC)

Extraction of Equivalent Circuit Models of Package Power Supply Distribution Systems from Full Wave EM Field Simulations Sigrity, Inc.

Frequency Dependencies of Power Noise Sigrity, Inc.

High Speed DDR Performance in 4 vs 6 Layer FCBGA Package Design Sigrity, Inc.

High-Level Simulation of Substrate Noise in High-Ohmic Substrates with Interconnect and Supply Effects Design Automation Conference (DAC)

High-Speed Design Challenges for a 1.4GHz Network Processor Signal Integrity Software, Inc. (SiSoft)

High-Speed I/O Design Considerations in Low-Cost Packaging Applications Toshiba America Electronic Components, Inc. (TAEC)

Impact of High Impedance Mid-Frequency Noise on Power Delivery Sigrity, Inc.

Integrated Modeling Methodology for Core and I/O Power Delivery Sigrity, Inc.

Leakage - and Crosstalk-Aware Bus Encoding for Total Power Reduction Design Automation Conference (DAC)

Managing Signal Integrity in Nanometer Digital Designs Cadence Design Systems, Inc.

Measured and Simulated Signal Propagation Behaviour on High Speed Nets ofLarge, Highly Dense and Complex PCBs Sigrity, Inc.

Measurement and Simulation of Simultaneous Switching Noise in the Multi-Reference Plane Package Sigrity, Inc.

Mid-Frequency Delta-I Noise Analysis of Complex Computer System Boards with Multiprocessor Modules and Verification by Measurements Sigrity, Inc.

Minimizing Peak Current via Opposite-Phase Clock Tree Design Automation Conference (DAC)

Modeling of the Electrical Performance of the Power and Ground Supply for a PC Microprocessor on a Card Sigrity, Inc.

Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops (24.2) Design Automation Conference (DAC)

Nanometer Sign-off: From Design to Manufacturing Cadence Design Systems, Inc.

Navigating Registers in Placement for Clock Network Minimization Design Automation Conference (DAC)

Noise Characterization of Static CMOS Gates Design Automation Conference (DAC)

Noise Considerations in Circuits and Systems Mentor Graphics Corp.

Noise-Aware Timing Analysis Cadence Design Systems, Inc.

On-Chip Measurements Complementary to Design Flows for Integrity in SoCs (22.4) Design Automation Conference (DAC)

Package and Chip Design Optimization for Mid-Frequency Power DistributionDecoupling Sigrity, Inc.

Partitioning-Based Approach to Fast On-Chip Decap Budgeting and Minimization Design Automation Conference (DAC)

PELE: Pre-Emphasis and Equalization Link Estimator to Address the Effects of Signal-Integrity Limitations Design Automation Conference (DAC)

Power Delivery System Performance Optimization of a Printed Circuit Boardwith Multiple Microprocessors Sigrity, Inc.

Receiver Characterization using Periodic Small-Signal Analysis Cadence Design Systems, Inc.

Signal Integrity Sigrity, Inc.

Signal Integrity and Clock System Design Integrated Device Technology, Inc. (IDT)

Signal Integrity Closure Cadence Design Systems, Inc.

Signal Integrity Comparisons Between Stratix II and Virtex-4 FPGAs Altera Corp.

Signal Integrity Sign-off Verification Magma Design Automation, Inc.

Simulation Study of Power Delivery Performance on Flip-Chip Substrate Technologies Sigrity, Inc.

Simultaneous Switching Noise and Signal Integrity Actel Corp.

SoC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects (38.2) Design Automation Conference (DAC)

Statistical Analysis of SRAM Cell Stability Design Automation Conference (DAC)

Statistical Logic Cell Delay Analysis Using a Current-Based Model Design Automation Conference (DAC)

System Level Signal and Power Integrity Analysis Methodology for System-In-Package Applications Design Automation Conference (DAC)

System-Level I/O Power Modeling Sigrity, Inc.

Top-k Aggressors Sets in Delay Noise Analysis (10.3) Design Automation Conference (DAC)

Via and Return Path Discontinuity Impact on High Speed Digital Signal Quality Sigrity, Inc.

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