Featured Articles

Go with the Flow for Power Integrity

Little additional evidence is required to make the case that power is the top issue for IC designers worldwide. But few completely agree on the precise nature of the problem, and fewer still know just what to do about it. In fact, power-aware IC design presents several interesting challenges, rather than just one "problem."

These myriad issues are best dealt with all at once, in an integrated, concurrent manner. Several of us have begun referring to this as a "power-integrity flow," defining a holistic method of addressing the relevant aspects of power at each design stage in an RTL-to-GDSII implementation flow.

Read the entire Sequence Design, Inc. article on SOCcentral.

On-Chip Power Integrity, Including Package Effects

On-chip power integrity effects and their influence on the entire power delivery system have become a major concern in the design of large and complex high-speed SoC designs. Today''s extreme design challenges require a complete power-aware solution that encompasses the global effects of the entire power delivery system, including the realistic effects of the package and the PC board on the functional operation of the IC.

There is a prevalent desire to closely link package-level and IC-level design processes so that package-to-chip and chip-to-package dependencies can be considered during the design process. The solution is a revolutionary co-design and co-simulation approach that simultaneously analyzes the entire power delivery network, from the PC board voltage supply, through the package power planes and pins, to the on-chip power grid, to insure the creation of operational designs.

Read the entire Sigrity, Inc. article on SOCcentral.

Placement-Driven Power Optimization at 90nm and Below

Today, chip designers are finding that traditional approaches to power reduction are no longer sufficient to meet their power goals. Enhanced clock gating, gate-level optimization, operand isolation, and multi-voltage design are helping to reduce dynamic power consumption. In addition, multiple-threshold optimization, state-retention power gating, and active-well biasing techniques are helping to reduce leakage power. But to achieve rapid design closure, designers still need something more: an EDA environment that takes advantage of placement information earlier in the design process.

This article looks at the power challenges arising in sub-90nm design that are taxing the capabilities of today's most comprehensive low-power flows. It then describes a solution that considers placement in a unified environment with logic and clock tree synthesis to enable fast, accurate power-efficient design at sub-90nm. Introduction

Read the entire Synopsys, Inc. article on SOCcentral.

Power and Timing Closures for IC and Package Co-Design

This paper discusses the signal and power integrity issues that are related to IC and package co-design, the methodologies to ensure timing and power closures, various EDA software, and several criteria to quantify the extraction accuracy. It is shown that the power/ground impedance corresponds to the worst-case simultaneous switching noise (SSN), and the best design for SSN is to have power bounce equal to ground bounce, or power/ground impedance equal to twice the signal-to-power impedance. To efficiently extract the power/ground impedance, a novel model-based full-wave extraction technique, using the fringe RLGC models, is also presented.

Read the entire Optimal Corp. whitepaper.