May 1, 2005 -- SOCcentral recently had Contributing Editor Jim Lipman sit down with Danny Biran, Altera's recently hired Vice President, Product and Corporate Marketing, to talk about what designers are looking for in FPGAs, structured ASICs vs. FPGAs, the role of IP, the changes taking place in the FPGA marketplace, and what the FPGA giant is doing to meet the challenges.
Lipman: What do you think will be the most significant issues FPGA vendors will face over the next five years?
Biran: The main issues fall into two categories. One has to do with the enormous opportunities that we now see. In the past, FPGAs were primarily used in a small number of applications. What we see now is a significant role in very high-end, high-performance, and high-density applications as well as in low-cost applications. We recently announced that we shipped a cumulative number of more than ten-million units of our Cyclone family, which is the low-end, low-cost side of our business.
Lipman: Is that all the generations of Cyclone?
Biran: No. Our first generation Cyclone family, which began shipping at the beginning of 2003, is completely rolled out. Our second-generation Cyclone II family began shipping in January and is not yet generating significant revenue yet, so that number is for the first generation Cyclone family only.
When we look at the requirements of the high-end and low-cost, cost-sensitive markets, there are some significant differences in their requirements. We have different architectures that we use: one for the Stratix II line, which is our high-density line, and another that we use for the Cyclone II family. Going forward, since we want to capture a large number of opportunities and a large number of markets, we probably have to have more supporting architectures.
The other issue has to do with the fact the FPGA industry is moving fairly quickly from one process generation to another, so Stratix II and Cyclone II are our 90nm products. We are already working on our 65nm generation and as we move to more and more advanced technologies, some of the tradeoffs between performance, cost, and power consumption become more difficult.
I wouldn't be surprised if going forward we will have to have more than one family for each of the low-cost and high-end markets because, again, we want to make sure that we don't compromise too much on performance, cost, and power consumption.
Lipman: You mentioned power consumption. How are you going to address power-sensitive consumer applications because, traditionally, FPGAs are not seen as a very power-efficient architecture for chips?
Biran: Even today, with the Cyclone and Cyclone II families, they are very efficient from a power-consumption perspective and the proof is that some of the applications in which they are used are in portable devices, such as cameras. These are the types of applications that were totally inaccessible by FPGAs before.
Having said that, when you look at power it's a problem that involves a number of different disciplines. Architecture has to do with power and cell design, and there are a lot of design techniques that help you with power consumption. Quartus II, which is our design software, is a very key part in our delivering our solutions to the market. The chip is one component; Quartus is another key component of the total product. The combination of the architecture, the circuit and the supporting software are all part of our solution, and power consumption is something that we are working very diligently on for our next generation.
Lipman: You talk about power being addressed in the design tools for the FPGAs. How about power as it applies to application software or firmware that is used on the chips? Are you working with any companies to be able to minimize power consumption by optimizing the software running on the devices?
Biran: You mean like software that runs on the Nios processor?
Biran: That's not a key area for power consumption. It's really more in the design software that configures the FPGA itself. Among the techniques that are fairly well known in the marketplace is making sure that you are using as few of the gates as possible and then the gates that you don't use do not consume power. There are various techniques to make sure that the gates are not consuming power.
Lipman: What about leakage in the gates that are not being used?
Biran: I was talking about dynamic power and some techniques to address that area. The other one [leakage] is at the process and the design-technique levels, another area that we are working very hard on. There are ways to make sure that transistors don't leak if they are not used, things that have to do with the transistor Vt, bias and other parameters.
Lipman: So you are looking are techniques such as back bias to reduce leakage power?
Lipman: Do you expect structured ASICs to take over much of the FPGA market and why or why not?
Biran: I definitely think that structured ASICs might take away some of the ASIC market. If you look at a structured ASIC, its basis is still an ASIC, so if you look at considerations such as development time and time to market, the characteristics of the structured ASIC are very close to those of an ASIC.
That being said, we do have our HardCopy offering, which is a structured ASIC. The thing that is unique about our approach is that you start with a design that is an FPGA, so you start with a Stratix or Stratix II design. Then, when you have enough functional verification and you are happy with the functionality of the device, we can seamlessly and in a risk-free way convert it to HardCopy or HardCopy II. When you do that, you significantly lower the cost and also significantly lower the power consumption and improve the performance. So, for us, we really see structured ASIC as an extension to the FPGA. We think structured ASICs are more competition to standard-cell ASICs.
Lipman: Can you give me a rough idea of the kind of cost reduction going from an FPGA to HardCopy?
Biran: When we talk about HardCopy II, which is our second generation and the one you go to from Stratix II, you're looking in excess of 90% cost reduction.
Lipman: Are there people who will go directly to HardCopy without doing an FPGA first?
Biran: Unlikely, since one of the challenges of ASICs is verification. One of the things you can do really well is to make sure that you do complete verification on the FPGA. It is just the most convenient platform on which to do verification. If you don't do it on an FPGA, you need to use tools such as formal verification or functional verification. These are very expensive and don't usually give you exhaustive coverage. We find that people use FPGAs for prototypes even if they eventually go to a standard-cell ASIC.
Sometimes customers make the decision that their target is HardCopy II when they start the design process, but they still need to go to an FPGA design for validation. There is no way to generate a HardCopy II device without going first to an FPGA. They may build only one FPGA, use it for the verification, and then go directly to HardCopy.
Lipman: So you're saying one of the reasons people will do this is because it is an easy path to go from a prototype device, an FPGA, into a production device, HardCopy.
Biran: Exactly. An FPGA is the best platform for doing verification anyway.
Lipman: How much consolidation do you expect in the FPGA industry in the next two to three years?
Biran: There isn't much left now and we don't expect things to change. Occasionally, we see startups being funded, maybe trying to create a new type of technology. Because of the need to have a compelling hardware and software solution, we really don't see any of these startups gaining traction. We don't expect any further consolidation -- we definitely expect the "duopoly" to stay pretty much a two-horse race.
Lipman: How about the possibility of some of the second-tier players getting together?
Biran: It's unlikely that our competitor will acquire one of the small guys. As for Numbers 3 and 4 getting together, I don't think it would make any real difference in the dynamics of the marketplace.
Lipman: Some of the other players beyond you and your main competitor have technologies other than SRAM -- Flash or anti-fuse. Do you expect non-SRAM architectures to survive and, if so, why?
Biran: I don't think that SRAM vs. non-SRAM will become a more important question than it is now. People are really looking for the right combination of the software, the hardware, and the IP - IP is becoming a very key consideration for customers. Since the non-SRAM technologies are owned by the very small players, I don't expect things to change.
If you look at our Stratix II family, we do have a very important security feature there. So, if one of the arguments against SRAM and for one of those non-volatile techniques was the security aspect, that one goes away with a device like Stratix. We now have encryption techniques that allow you to encrypt your bit stream. As a result, you protect the IP and the design of the FPGA. So, even to the extent that security was something that leaned towards non-volatile techniques, that one is going away with the type of security we are now providing.
Lipman: Are you using any of the standard encryption algorithms?
Biran: Yes, we use AES.
Lipman: Where do you think embedded FPGA arrays are heading? Do you think they serve a purpose and that people will adopt them or is it just a fad?
Biran: I think it is a fad. Their basis is still an ASIC with all the issues of an ASIC. You have the risk, the long development time, and the very high development cost. One challenge that people don't always realize is that since FPGAs have very different design flows than ASICs, marrying the two is a lot easier said than done. One example is timing closure. The reason is in an ASIC, you have a given, fixed path you need to close timing on. In an FPGA, by definition, you don't know what the final functionality will be. So, timing closure is significantly different.
There are a variety of issues that are very different in the FPGA space than in the ASIC space. Where an embedded FPGA might make sense is where you have a device that is primarily an ASIC and in a given, small area you need some field programmability; here you may benefit from something like an embedded FPGA, but that's usually a niche application. We definitely don't see embedded FPGAs in ASICs as a threat since it doesn't change the fundamental issues of an ASIC-development cost, development time and risk.
Lipman: How critical is IP to your continued growth and success?
Biran: One thing we look at is how many of our FPGA customers use IP cores. If you look at FPGAs as opposed to CPLDs, a growing percentage are using IP cores. We definitely think that providing these cores will be very significant.
Lipman: What percentage of your customers use IP cores?
Biran: It is definitely higher than 50% and going up. We see increasing sophistication in the use of our Nios core. More and more customers use multiple Nios cores on a device. We also see a lot of demand for the interfaces-PCI, PCI-X, PCI Express-in FPGA applications, and we see this increasing in importance going forward.
Lipman: Do you think there will continue to be a mix of hard and soft IP cores in an FPGA?
Biran: There will be a mix, but you want to make sure that you still only use a hard core in things that are very widely used. If you look at our Stratix and Stratix II families, we have what we call the Stratix GX version; in those families we embed transceivers. Transceivers are something that are widely used in a variety of applications-adding them as hard cores can definitely add value. At the same time, hardening something that people may not want to use in the way you hardened it only adds to the complexity and takes away some of the value of an FPGA. There will be a mix [of hard and soft cores], but one has to be very prudent about what you harden and where it is on the device.
Lipman: What markets do you think offer the largest growth potential for you?
Biran: I don't consider, necessarily, specific markets because now we are in every market. I think the main opportunities are in capturing more and more value of the system. We talked earlier about Nios gaining more popularity. We definitely see more systems where we take at least some of the computing tasks. Maybe you still have an external processor, but more of the compute tasks are going to be off-loaded to the FPGA. They could be off-loaded either to a sea-of-gates or to a Nios or a variety of Nios cores.
The same thing with DSP. We see a lot of places now where FPGAs clearly have performance advantages over a traditional DSP core. So, you may not totally replace the DSP processor, but you would offload some of the more compute-intensive tasks to the FPGA. Therefore, it's not a case of going into new markets, but capturing a bigger part of the system in the markets in which we are in already.
Lipman: What do you consider your main markets right now?
Biran: Communications is still, by far, the biggest one. Within communications, it's wireline and wireless. We see a lot of momentum in 3G base stations, but also in telecom and in enterprise networking. With all the growth in consumer, we are also experiencing nice growth here. Because of ASPs, communication is still our biggest market with industrial in second place.
We also do very well in displays. We are in a variety of portable applications -- video cameras, still cameras, and devices of that nature. But, displays are definitely a very key area for us.
Lipman: Thanks for giving SOCcentral the opportunity to present your views.
Danny Biran joined Altera in January 2005 as vice president, product and corporate marketing with over 20 years of semiconductor industry experience. Most recently, he served as the president, CEO, and member of the board of directors of Silverback Systems, a privately-held company that develops silicon solutions for storage networks. Prior to that, Biran held vice president and general management positions at LSI Logic and several engineering management and marketing positions at National Semiconductor. He holds BSEE and MBA degrees from Tel Aviv University.
Go to the Altera Corp. website to learn more.