August 4, 2005 -- Automated synthesis-oriented digital integrated circuit (IC) design methodologies have revolutionized the semiconductor industry over the past 25 years. Historically, use of precharacterized and silicon verified "standard cells" was driven by the designers' need to design and verify large digital circuits using limited resources – transistor-level design and verification is simply too resource-intensive to be commercially viable for most digital designs.
However, from its inception, "quality" of the designs created by such automated standard-cell based design flows, has been deemed "poor to barely acceptable," by almost any measure of quality including clock speed, area/die-size, power consumption, etc.
In a series of studies including a special session at the 37th Design Automation Conference, it was estimated by various researchers that designs created by such automated design flows are slower by at least a factor of 6 and larger in design area by at least a factor of 10, when compared to similar designs created and/or optimized manually. It was shown further that a significant portion of the deficiency in quality – e.g. a quarter or more of the speed shortfall – can be attributed to the use of a fixed, pre-defined library of standard cells. This deficit in quality has led to a severe timing closure problem that grows worse with every new process generation. As far back as in 1999, when 180nm process was still new, surveys done by Collett International showed that greater than 60% of all ASIC designs had timing closure problems. The problem has become significantly worse as fabrication processes progressed through 130nm and 90nm process nodes to 65nm process node of today.
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