June 9, 2006 -- To become the third major supplier of FPGAs, Lattice developed a product strategy that focused on superiority to Altera and Xilinx in key areas. Our larger competitors often maintain that there is no need in the market for a third major FPGA supplier. However, based on customer reception of our 130-nm and newer 90-nm FPGA products, our strategy appears to be working, and that customers value the unique technologies Lattice provides.
Lattice has launched five programmable device families in the last two years: the 130-nm and 90-nm SRAM-based LatticeECP families; the 130-nm SRAM plus Flash LatticeXP and MachXO families; and the 90-nm SRAM LatticeSC. Each of these families is targeted at specific market segments:
- LatticeECP is targeted at the very price-conscious, low- to medium-density Low Cost FPGA segment; LatticeXP and MachXO at the Non-Volatile FPGA segment.
- LatticeSC is targeted at the high-density system chip, or "platform," FPGA market, where embedded SerDes and performance are the keys to success.
In each family, Lattice delivers unique performance or features for devices in its class, such as the best pre-engineered DDR and DSP capability in LatticeECP devices; non-volatile, instant-on operation in LatticeXP and MachXO devices; and the lowest power FPGA SerDes, 2-Gbits/s LVDS I/O, and system-level hard IP functions in the "Extreme Performance" LatticeSC. Each family is available at very attractive price points.
Lattice calls its approach to implementing hard IP functions on-chip “MACO,” for Masked Array for Cost Optimization. The integration of FPGA and ASIC structures into a single architecture is perhaps one of the most dynamic areas for system-level FPGA evolution. Combining very fast, dense, low power structured ASIC blocks with the flexibility of FPGAs potentially yields a more optimal implementation of many logic functions. To achieve that implementation, however, the end application(s) must be targeted as the devices are architected, and the balance between FPGA and ASIC blocks on-chip must be carefully considered.
In the LatticeSC FPGA architecture, for example, high-performance communications was the application space driving many functional trade-offs, so the devices not only have up to 32 SerDes channels and 900 general-purpose I/O per device, but also dedicated hard Physical Coding Sublayer (PCS) and other protocol controllers (e.g. SPI4.2, PCI Express, Ethernet) that optimize performance and power for these applications. The FPGA and ASIC resources on the devices were carefully balanced so that there are approximately the same number of ASIC and FPGA logic gates on each device. Combine these blocks with a soft RISC-based microprocessor core and other peripheral blocks built into the FPGA fabric, and the era of true system-on-chip has arrived.
In addition to Simple PLD, Complex PLD and FPGA programmable logic devices, Lattice is also, uniquely, a supplier of solution-specific Mixed Signal PLDs that target the common board-level design problems of power management and clock generation. Lattice's Power Manager series merges CPLD technology for complex power supply sequencing with programmable analog blocks such as D-to-A and A-to-D converters, FET drivers, voltage comparators and the like to provide an integrated solution to monitor, sequence and manage multiple power supplies on a PCB or in a system. The ispClock family generates up to twenty unique clock outputs operating at up to 400-MHz frequencies, each output having its own programmable delay, interface standard and frequency (up to 5 derivative frequencies can be generated on chip and can be distributed to any output). So, Lattice is not just in the programmable device business, but in the programmable system solutions business as well.
Of course, unique silicon is only half the competitive battle; design tools, IP support and applications knowledge also are essential to get customer designs to market quickly. Through a combination of internal development, strategic acquisitions and partnerships, Lattice has the expertise to bring an extremely competitive design methodology, as well as comprehensive system-level design support, to the market. In addition, given our 20 year-plus involvement in the programmable logic business, Lattice has a proven track record as a reliable partner that supports our customers throughout the life cycle of a design and their end product.
Nothing remains static in our industry for long: 65-nm technology looms as the next technology step, moving into production next year. Lattice is fortunate to have a superb foundry partner, Fujitsu, Ltd., working with us to realize our architectures in silicon. Fujitsu's non-volatile Flash technology expertise and track record is an added edge for Lattice as we strive to "out innovate" our competitors. This partnership is driving Lattice's FPGA architectures rapidly to the trans-100K LUT range.
Gordon Moore once forecast that silicon gate capacities would grow so rapidly that system designers would not know what to do with all that silicon horsepower. Frankly, I don't think we'll confront that problem in the world of FPGAs anytime soon.
By Stan Kopec.
Stan is Corporate Vice President of Marketing, Lattice Semiconductor Corp.
Go to the Lattice Semiconductor Corp. website to learn more.