February 26, 2007 -- Despite warnings of dire consequences and tales of chips not fitting their packages, not nearly enough attention has been paid to IC package and chip co-design. And, I'm inclined to believe that this will persist because design teams continue an ad-hoc approach to chip-package co-design. To be sure, the problem extends across multiple boundaries and multiple disciplines within system design, from the die to the package and the printed circuit board (PCB). I contend that it's the chip designer who must take responsibility and begin to consider the way his or her chip fits in the environment.

A chip designer should think more like an architect. Before committing the sketch to paper, the architect knows the environment — from the plot line of the property where the house will sit to the general size and dimensions of the house. Details such as room layout and size, heating and electrical requirements and where the plumbing goes come next. It's a systematic approach that takes careful planning and tools to get the job done correctly.

Like the architects who began moving from hand drawing to AutoCAD in the 1987, chip designers are finding that traditional methods that rely on spreadsheets for optimization decisions are no longer adequate.

While we can be critical of a design team, it's actually the move to smaller process geometries and higher performing chips with higher levels of functionality that has caused ill-fitting chips in their packages. This means escalating design and fabrication costs as chips now include greater numbers of pins, more I/Os at accelerated speeds and mixed analog and digital technologies. Chips have more power distribution challenges, higher frequencies, more demands on power plane integrity and issues related to simultaneous switching output (SSO).

And finally, more chips are now jammed into a single package, creating the need for new technologies such as system-in-package (SiP), 3D packaging with stacked dies and 3D transistors. All serve as alternatives to systems-on-chip (SOCs) on a single die.

These design trends point to the obvious need for IC package and chip design to be done concurrently, along with the need for chip designers to rethink their orientation and become more like architects. In today's world of chip design, floorplanning of the chip and placement of I/Os cannot be done in isolation.

The stage, then, is set for a concurrent design methodology for chip and package, allowing for full-chip integration early in the design. Chip designers need to incorporate package-aware optimization and tradeoff software into their design plan to test how a signal propagates through the die, the package substrate and the PCB.

This is not to suggest that chip designers need to become packaging experts, though they should understand some long-ignored packaging concepts. Instead, this methodology would offer them packaging guidance that's built into the design tools.

Tools are becoming available to bridge the gap between the design of high-performance ICs and packages, and a chip's integration with the rest of the electronic system. This approach offers chip designers the ability to make optimal I/O tradeoffs between the chip layout, wires within the package and PCB connections. It's able to accept various constraints from diverse design domains including PCB, package and IC, giving designers the ability to simultaneously visualize the chip in the package ensures design convergence. The result is optimal placement of I/Os, associated logic, bumps and routing on the top layer from I/Os to bumps.

As an example, the design of an SOC would start with an estimate of the number of I/Os and a set of performance requirements. Determinations are made on the number of power and ground nets, escape patterns and power delivery for flip-chip ICs, and the wire-bond pattern for wire-bonded chips. With this information on the package I/O assignments, the package engineer can create the initial package layout, which is near the beginning of the design flow. I/O planning enables a departure from the traditional sequential design of chip and package to a concurrent design approach, shaving weeks from the production schedule.

With widespread deployment, tools such as these will ensure that every chip designed fits its electronic system just as a house fits its lot. Along the way, good I/O performance is ensured for signal integrity, power integrity, physical implementation at a lower cost. And at last, chip designers will be thinking and working like architects, and not resort to an ad-hoc approach.

By Egino Sarto, Chief Technology Officer, Rio Design Automation, Inc.