July 19, 2007 -- For the last couple of years, there has been extensive discussion about the use of statistical static timing analysis (SSTA) in the verification of current and future generations of IC designs manufactured at 90nm or below. Given the combination of physical effects and complexity in the most advanced processes and designs, timing verification needs to account for intra-die and die-to-die variability in manufacturing. Including voltage and temperature margins in the analysis adds complexity to the verification task and has resulted in the explosive growth of the number of design "corners" to be analyzed. Tens of analysis runs that take many hours to complete make timing sign-off a real challenge. And, at the end, there are still questions of whether pessimism could have been reduced or the yield will be acceptable.

Compared with traditional corner-based static timing analysis, SSTA offers several advantages. Most notably, it provides a more realistic estimation of timing relative to actual silicon performance. In addition, SSTA — in just one or two runs — can report all of the process, voltage, and temperature effects that influence design timing and displays the yield that can be expected. Armed with better and more complete information from SSTA, designers can focus their optimization efforts on the timing paths that have the biggest effect on overall performance and yield, rather than paths that may fail only at extreme corners.

Meeting timing at the worst- or best-case corner can be very challenging; often lengthens a design schedule; and increases power consumption of an IC. With a large range of potential delay values — often as much as 50% or more between the slow and fast process corners — it becomes more difficult to meet both set-up times at the worst-case corner and hold times at the best-case corner.

Even if the performance goals are met, there are often undesired effects on other design metrics, in particular, on power consumption, noise immunity, and leakage. For example, to meet an aggressive performance target, optimization may deploy a higher ratio of low-threshold cells that are faster but have a bigger power footprint. With statistical analysis, a better trade-off between timing and other design metrics such as power and noise immunity can be achieved.

SSTA provides a list of worst timing paths, and, uniquely, gives the probability of those paths failing while accounting for the effects of process variation. To accurately predict variation, SSTA accounts for both systematic sources, such as lithography, and random sources, such as doping.

Even within the same chip, there is a wide range of on-chip variation (OCV). Traditional static timing tools use guard-bands or OCV factors (often as much as ±15%) to safeguard against OCV. However, this type of over-design is too wasteful to be effective at 65-nm and below. This is because, at the smaller geometries, the process is more sensitive to variation, and over-design has an even bigger effect on power leakage. In addition, many of the advantages of using a costlier process node may be eliminated if too many cells are needlessly over-sized to meet an unrealistic OCV target.

SSTA can help provide a much more realistic measurement of OCV, one that reduces the overall guard-band and protects against corner cases where a single, large OCV factor is not sufficient to catch potential errors. This is because, depending on its size, location, orientation, interconnect loading, and how it is driven, each transistor in the design will have a unique sensitivity to each source of process variation.

So, there are three main advantages to SSTA compared with traditional corner-based analysis. First, pessimism in the design is reduced. Possible reduction of path delays by 10 to 15% can lead to lower power consumption. Second, timing sign-off can be achieved more quickly with the dramatically faster speed of analysis. Third, different scenarios and implementations can be more quickly explored to understand yield, performance, and cost trade-offs.

Intelligent corner selection vs. SSTA

In the conversation about timing analysis, one integrated device manufacturer has suggested that "intelligent" corner selection could be done in lieu of SSTA. In the special case of microprocessor or custom design — where a deep understanding of process and environmental conditions is available by having a long design cycle, large design teams, and the use of binning for the manufactured parts — intelligent corner selection is workable. For smaller ASIC teams that are dealing with different synthesized designs and a fixed performance target, the corners for analysis are design- and even path- dependent, so choosing the correct intelligent corners is not easy. For those design teams that want to choose intelligent corners, SSTA would be the ideal tool for deciding what those corners should be.

In general, designers are not familiar with handling probability distributions. However, they are still interested in determining how much pessimism exists; whether a design is robust; and what optimization of power or performance could be done. Designers typically ask themselves, “Given my target spec and my timing report, where can I make improvements?” Now, they must also ask, “How can I improve yield?” SSTA is a tool that can deliver the answers.

The easiest way for design teams to begin working with SSTA is through a phased approach. Statistically-aware timing analysis can be used for analyzing corners in a traditional deterministic flow, and for analyzing some of the random and systematic variations that affect performance and yield. Because SSTA is engineered to run verification so quickly, analyzing multiple modes of circuit operation is also practical. With all of its capabilities, SSTA is, in fact, a superset of corner-based approaches that are variation-aware.

To use SSTA fully requires statistical library characterization and layout extraction. New methods for library creation that deliver 10X breakthroughs in characterization speeds over traditional library tools make practical the creation of statistical libraries. This, combined with new standards for describing statistical information, gives CAD teams a clear path for adopting a statistical characterization flow.

While systematic variations do not have to be modeled in SSTA, there are advantages in doing so. For IDM design teams, they get an additional way to understand the performance trade-offs for their designs, particularly as new processes are being developed. Because SSTA is a general solution that can display the analysis for both systematic and random variations, it can also determine how each kind of variation affects the overall performance of the design. The consensus for leading-edge silicon nodes is that random or mismatch variations will very soon become dominant and this will require the use of SSTA.

At 45-nm, silicon node design teams will need to adopt SSTA as a part of their design-for-manufacturing (DFM) infrastructure to control process variability in design. Design tool developers are working to create an architecture and platform that delivers all the benefits of SSTA, the execution speed and capacity to handle the expanded set of calculations, and applicability to many different types of designs, such as wireless, graphics, and low-power. This is why the adoption of this new generation of timing sign-off is increasing.

By Dr. Mustafa Celik.

Dr. Celik is Chief Executive Officer, Extreme DA. He formed Extreme DA after holding leading technical positions with Magma Design Automation and Monterey Design Systems following his post-graduate work at Carnegie Mellon University. Dr. Celik has extensive experience in the research and development of IC timing and extraction technology and methods.