June 9, 2008 -- Once considered a veritable "black art" practiced only by voodoo cults (and advanced microprocessor designers), low-power design methodology has become a mainstream requirement for modern IC design. Initially, basic clock-gating gained popularity, where design teams could keep track of power domains and state transitions through the wizardry of spreadsheets, scripts, and makefiles. Soon, however, design teams graduated to more advanced techniques necessary to meet power budgets, further complicating manual kludges to the breaking point. In 2006, the industry aligned upon a critical need for a standard to specify "golden" low-power design intent, analogous to golden functional intent as defined in today's HDLs.

One effort, the Common Power Format (CPF), had already been developed, iterated through silicon testing among a dozen companies, and then eventually contributed for open standardization through Si2's Low-Power Coalition (LPC) late in 2006. A second effort, the Unified Power Format (UPF), was drafted under Accellera, then transferred into IEEE-SA in early 2007, where draft development continues under the p1801 work group. There has been concern over multiple competing formats, not unlike the EDA history of competing library formats and HDLs.

It is, of course, significant that CPF v1.0 has long had production support at every major foundry and IP provider, well over 100 real design tape-outs, and dozens of public success stories. It's also significant that the upcoming CPF v1.1 is expected to contain over 100 pages of key enhancements when released in the coming few months. Yet the focus on competing file formats runs the risk of distracting the EDA industry from the big picture. It would be wrong to assume, that by simply standardizing some file format, we will solve all the significant issues in low-power design that must be addressed over the next several years.

While EDA tools will provide the needed algorithms, the ability to connect them with the necessary data supporting advanced low-power techniques demands standards that enable these techniques. However, industry cannot standardize what it cannot prioritize, and it cannot prioritize what it does not understand. Even terminology used at different leading design houses can have different or vague meanings, as well as specific data that must also be semantically aligned before being effectively standardized.

The Low-Power Coalition, an impressive lineup of industry leaders spanning IC design, IP, and EDA, is at work defining next-generation priorities for low-power design flows, along with the necessary standard interfaces to enable working solutions. LPC members recognized the need for common terminology, and for documenting every known low-power design technique, as a prerequisite to specifications involving the most advanced low-power concepts.

The LPC members have structured themselves into several distinct working groups (WGs), coordinated by a technical steering group (TSG). The Flow WG addresses tool flow-related issues, and is aligning on a (future) power-aware reference design flow spanning ESL through GDSII. The Data Model and API WG is focused on clean semantics for all low-power data objects and their relationships to one another to ensure inter-operable, scalable, and extensible standards. The data model serves as the foundation for defining a software API standard, particularly useful for incremental “what-if” analyses. The Format WG specifically addresses enhancements to the CPF standard, presently editing the draft for CPF v1.1.

One special function of the TSG is to maintain the industry's low-power roadmap. The first release of this roadmap (downloadable from the Si2 website) has already been made public. Below is a summary advanced low-power roadmap.

Power Modeling – It's clear that shifting DVFS modes impact signal timing, just as PSO states affect functionality, manufacturing test, and verification. Similarly, we know that insertion of level shifters constrains placement and routing (and also affects timing optimization). Yet what about the added variability due to DFM concerns, or the impact of foundry process re-targeting? How should power network components be represented, and where? What additional power modeling will be required to deliver working silicon as these additional variables come into play? System-Level (ESL) – System architecture plays a critical role in overall power consumption, as does the selection of IP content and hardware/ software implementation decisions. Embedded software is already a major determinant of dynamic power consumption, and this role will only increase over time. How do we move the analysis and the optimization space up to the architecture and system level, where arguably 80% of the power management opportunity sits waiting to be exploited? How can we stretch our thinking to encompass power-aware software design? Rapid "What-If" Power Optimization – If you find a problem and make a change, what is the impact of that change on critical path timing, signal integrity, and die area? How long will it take you to find out so you can try a different approach, if necessary? Is this an optimal choice — or at least better than your competition? Design flows will require a more rapid incremental "what-if" capability. But to permit interoperability, this means enhancing standards for an API interface that tools can exploit to exchange power details (such as budgets, requirements and constraints) in a quick and incremental fashion. Advanced Design Techniques – How well do today's low-power standards support emerging low-power needs? Do these standards scale easily for large designs and varying power profiles? In the years to come, there will be innovations in low-power design. Many of these advancements will require improvements to standards that communicate low-power information across the flow. Whether you are using pulsed clocks, adaptive biasing, DVFS, or just trying to import an IP block that does, you will depend on continued advancements in low-power techniques – including standards that enable interoperability.

These are just some examples of the critical issues regarding learning and growth in the industry. As anyone can see, the real lesson of modern IC design is that everything is connected. No one can make design changes for power optimization without regard to its impact on routing, timing, signal integrity, DFM, and so on. Furthermore, while we standardize current practice, novel techniques and methodologies are continuously being developed, but may not yet be inter-operable or commercially supportable.

We are hardly finished in low-power design. Much more lies ahead if we are to be successful at continuing the advances of Moore's Law and functional integration in ICs without hitting unyielding barriers that threaten our progress. Every designer and developer is a stakeholder in the outcome of these efforts.

The members of the LPC and Si2, invite you to join us in defining our future for low-power design. It is time to leave behind yesterday's EDA “format battles” and instead place our focus on the larger challenge before us — to advance low-power capability in a much more fundamental and substantial way. This is a destiny we all share and the task is too large and important to leave in fragmented form. We must develop a stable standard, so IC engineers can concentrate on low power design without worrying about which format will prevail.

By Steven E. Schulz, President and CEO, Si2

Steve has served as President and CEO of Si2, the leading worldwide consortium of semiconductor and software companies chartered to develop EDA standards, since 2002. Steve was previously VP of corporate marketing for BOPS Inc. and was employed by Texas Instruments for 19 years. At TI, Steve was a Senior Member of the Technical Staff and held a wide variety of management and technical positions, including CAD strategy manager and reliability strategy manager. Representing TI, he served as chairman of the Design Sciences Technical Advisory Board for Semiconductor Research Corp. He has served as President of VHDL International, Co-chairman of Accellera, and Chairman of the VITAL and SLDL/Rosetta standards initiatives. He has authored more than 150 articles on EDA and IC design methodology.