October 6, 2008 -- As process nodes shrink below 90nm, the importance of test increases dramatically. Smaller feature sizes mean more gates, which translates to the need for more test structures and increased manufacturing tests. Problem is, tester time is more expensive than ever (what isnít?) and power, timing and performance are often at odds with the need for extensive test structures inside an SOC. As a result, engineers are turning to design-for-testability (DFT) to take advantage of EDA tools that ensure adequate coverage and reduce test costs, without impacting design goals or sensitive time-to-market windows. EDA companies are striving to improve test synthesis and automatic test pattern generation (ATPG) techniques to accommodate soaring gate counts. Other companies rely on logic built-in self test (BIST) to meet design and test goals.
"There are several factors making test more challenging at smaller geometries," says Robert Ruiz, Product Line Marketing Manager, Test Automation Products at Synopsys, Inc. "First of all, there are simply more gates, which means multiple test patterns. A few years ago, detecting random defects was sufficient, but now defects are more subtle. They result from systemic defects, complex component interactions, lithography and other process variations. These are much more difficult to capture, so ATPG technology has to evolve. In addition, everyone has to manage costs, such as time on the tester and engineering time spent on developing tests, which can affect productivity. The EDA industry is trying to juggle all of these needs at once, while making DFT as automated and easy to use as possible. This is important, because design engineers are really hired to improve functionality and performance, not spend time on DFT."
Low power strikes again
In addition to ease-of-use, EDA vendors must consider other factors that enter into the DFT equation, such as low-power design. Power budgets are developed with the assumption that not all portions of the design will be on at once. To meet coverage goals, however, traditional test often kept more of the chip switched on than would ever need power in a normal functioning state. As a result, power budgets were often exceeded. Some EDA tools let designers and test engineers partition the chip for test so not all portions of a chip are on, which keeps power budgets intact. But manual intervention is necessary, and that can impact productivity. EDA vendors say theyíre working on automating this step, as well as using other power-savings methods such as clock gating. Newer DFT tools gate clocks, so only the ones necessary to test a portion of the design are on at any given time, which saves power.
Figure 1. This diagram compares two profiles of scan flop switching activity during capture mode for a design, with each dot representing the percentage of total scan flops that switch during capture mode for each pattern. Assuming the peak switching activity of the design's mission-mode patterns is near 23%, then standard scan ATPG (red data) produces a significant number of patterns that exceed this peak. If the power rails are not designed to accommodate the instantaneous switching currents caused by these increased switching levels, then the additional IR-drop delays could lead to yield loss during testing. To circumvent this problem, the designer can specify a flop switching budget as an input parameter to TetraMAX power-aware ATPG. The tool attempts to observe this budget every time it generates a scan pattern, as reflected by the green data showing flop switching activity when the budget is 23%. Source: Synopsys, Inc.
Compress for success
Excessive power consumption can also result from the sheer size of the test patterns that must be used to provide adequate coverage. Thatís because traditional methods of test, such as stuck-at faults, are no longer adequate for todayís complex deep-submicron designs. Test engineers now need to run at-speed tests, which complicates things.
"At-speed tests increase the number of test patterns by a factor of 3X to 5X," says Greg Aldrich, Director of Marketing, DFT at Mentor Graphics Corp. "To speed it up, we employ compression technology, which uses on-chip hardware. Our solution embeds a small piece of logic in the design. It takes a small set of input patterns and expands that internally. On the output side is hardware that compresses that data into a small signature to send to the tester. To the tester, it just looks like a smaller design with a smaller set of constraints. Internally, the on-chip hardware expands the patterns to adequately test the design. Itís a combination of the hardware and the ATPG software that works together to ensure proper coverage. We get test data and test time compression on the order of 150X today without impacting coverage.Ē (Learn more about memory test strategies by reading the Mentor Graphics article Electrical Fuse Makes Repairable Memory Testing Easy.)
Figure 2. Embedded compression with TestKompress introduces a small amount of circuitry to the design (via RTL-level IP insertion) that expands compressed test patterns taken from the tester, applies them to the DUT, and then compresses the test results for output back to the tester. According to proponents of this technology, the embedded compression circuit works with ATPG software to deliver a 100X reduction in test times and data volume with no loss of test coverage. Source: Mentor Graphics Corp.
Test pattern complexity is also changing the way that test is used. As previously noted, stuck-at fault tests are no longer adequate at 90nm and below. To catch defects that could slip by traditional stuck-at tests, EDA vendors are using more sophisticated methods to find small delay defects in the design.
"Weíve invested in technology that can detect these defects," says Synopsysí Ruiz. "Itís better than normal at-speed testing, because at 90nm and below, there are some subtle defects that arenít caught. Thatís because traditional at-speed tests find a fault in a very simple manner. Think of a portion of the design where the clock is a starting point, with some combinational gates in that path that lead to some flip flops. The traditional at-speed test looks for the simplest path. We came up with technology that examines the longest path through the combinational gates. If that defect causes a small amount of delay, then going for the easiest path wonít detect that. So weíve come up with small delay defect test to find those that will cause a tiny bit of timing delay. To do that, we used our static timing analysis tool, PrimeTime. It looks at cross-talk analysis, points out the effects on the clock line, and uses that to guide Synopsysí TetraMAX ATPG to target those small delays. Using this technology, STMicroelectronics was able to capture more defects than with any other type of test. It was able to catch 60% of the defects exclusively using the small delay defect technology." (Learn more about problems finding small delay defect by reading the Synopsys article Small Delay Defect Testing.)
Getting a jump start
Some EDA vendors are tackling DFT issues in the earlier phases of the design cycle by focusing on RTL. They say that analyzing and fixing weak areas at the RTL can help designers pin-point problems early on, which can help them avoid costly iterations.
"We analyze the design and tell the customer where the RTL could affect the quality of test," says Kiran Vittal, Product Director at Atrenta, Inc.. "We identify the lines of code that could impact test coverage, whether static or dynamic, and provide a test-coverage estimate. Unlike scan technology, we donít modify the RTL. We analyze the RTL and give the designer a report. The designer can then fix the RTL to get better coverage. We show the areas of code where test can be improved with a link to the schematic so you can see exactly where the problem is on the device. We are different than other EDA providers that see test as a back-end process. We believe itís better to bring test to the designers because it can save expensive and time-consuming iterations. One of our customers used ATPG and found a bug during test. The engineer had to go back to the RTL, change it, re-synthesize the design, re-implement scan, generate a netlist, then run place-and-route. That took them four weeks. If they had caught that defect at the RTL, they wouldnít have had to perform that iteration."
Figure 3. Atrentaís SpyGlass-DFT test coverage estimates are highlighted in blue (bottom window). The upper right window shows a link to the schematic with areas that affect test metrics highlighted in red. The upper left window shows the RTL that should be modified to improve coverage.
Traditional methodologies updated
Though many EDA companies are focusing on RTL and ATPG compression to get complete coverage, other companies are relying on tried-and-true technologies such as built-in self test (BIST) to find, analyze and fix bugs in the design. Proponents of BIST say that even with ATPG compression, test vectors for large multi-million gate designs become prohibitively large. These enormous test suites take expensive tester time and can slow design debug. As a result, there is a growing gap between tapeout and getting working samples to the customer. BIST proponents also cite complications in the growing use of high-speed serialized/deserialized (SerDes) I/O as well as the exponential growth of memory in todayísí system. Taken together, BIST advocates say these factors translate to an inordinately large number of test vectors, which will only continue to grow at ever smaller process nodes.
"Any test strategy will probably get you to where you want to go, but itís a question of how efficient and cost effective it is," says Stephen Pateras, Senior Director of Strategic Technology at LogicVision, Inc.. "Designs are now up to 80 million gates or more. ATPG compression is okay here, but itís a one-time savings. Even with compression, the test patterns grow over time, so the savings donít scale. Because BIST is embedded in the chip, you can add more and more BIST as your design grows, which means it is fully scalable. So the test time is pretty much stable, no matter how big your design is."
Logic BIST also saves tester time, proponents say, because the test occurs on chip, as opposed to going off-chip to a tester then coming back on chip. In addition, there are "bring up" costs, which is the time it takes to test and debug chips before working samples can be released.
"You have to get the tests up and running, debug, and make sure all portions of a device are functional before you can ship to a customer," Pateras continues. ďThis can take days or even weeks. Without exaggeration, we can provide the same level of coverage in a few hours. The reason is that all the BIST is fully verified before you tape outóthereís no fixturing, no timing and no interfacing. Another factor that affects test time is the growing size of deep submicron designs. If you go from 1 million gates to 10 million gates, your ATPG patterns increase tenfold, which increases costs. With BIST, you go from one BIST controller to 10 running in parallel, and thereís no real increase in test time. As far as the argument that logic BIST takes up too much area, itís actually ceasing to be much of a factoróit tends to be 3 to 4% of the logic. So if you have a million gates, you need 30,000 to 40,000 gates for logic BIST. That 3% to 4% number is fairly constant, regardless of the size of the device." (Learn more about BIST and test by reading the LogicVision article Maximizing Test Efficiency with BIST.)
Some companies are taking advantage of other tried and true methods, like JTAG, to measure and analyze a deviceís performance. ASSET InterTech, Inc., for example, built its business by testing interconnect and high-speed I/Os at the PCB/device level. Recently, the company announced it is positioning the company, its products and its technologies to provide open tools for embedded instrumentation in design validation, test and debug applications.
"As physical access to logic pins and I/O gets more difficult, engineers are finding that traditional instrumentation such as logic analyzers and oscilloscopes are getting harder to use," says Glenn Woppman, President and CEO of ASSET. "As a result, the IC companies are using on-chip instrumentation like power and signal monitors for better visibility into the chip. ASSET will continue with JTAG structural test while developing open embedded instrumentation solutions, which is emerging as the most viable and efficient way to perform design validation, test and debug. In general, the trajectory of the industry has been moving toward non-intrusive methodologies for more than 15 years, ever since boundary scan technology came on the scene. Embedding instrumentation is the next logical step and over the last several years we have been migrating our ScanWorks product into a role as an open platform for embedded instrumentation, including boundary scan, CPU-emulation functional test, Intel IBIST and others."
Test: A simple term with many facets
For years now, design and test engineers have grappled with balancing the amount of coverage they need to get a reliable system out the door. Too much time spent on test ensures complete coverage, but may delay tight time-to-market goals. Too little test can lead to everything from costly iterations to catastrophic failures in the field. With the constant evolution of traditional technologies such as JTAG and BIST, along with advances in ATPG compression and test automation, test may make the coverage/ time-to-market balancing act a bit easier. One thing is clear. Design engineers must get more involved in moving DFT into their arsenal of EDA tools. Simply producing a design that meets timing, power and cost goals may not be enough. With some effort, designers can create a chip thatís ready for test. This will help ensure that coverage and time-to-volume goals are met and that next-generation versions of a chip will start with a fully tested and bug-free design.
By Mike Donlin, Senior Editor, SOCcentral.com