June 1, 2011 -- As system-on-chip (SOC) designs continue to increase in size and complexity, the verification task becomes the bottleneck that can take up to 70% of the overall SOC development effort. As a result, any method that can help to reduce verification cost and achieve verification sign-off earlier is of great interest.
A case study at this year's Design Automation Conference by Taiwan Industrial Technology Research Institute (ITRI) describes an innovative approach to dramatically increase the verification efficiency of a custom-designed FPGA-based prototype board by automating existing in-circuit emulation capabilities and enabling a high-level of visibility into the FPGA(s). This FPGA-based SOC verification platform is a promising new area of interest for ITRI, which is responsible for supporting Taiwanese industry research and development of new technologies and methodologies related to IC design. (See DAC 2011 User Track 2U.7, "A Case Study on Adopting a Flexible FPGA Verification Methodology.")
A high-performance multimedia SOC platform
The SOC design is a high-performance Android-compatible multimedia SOC platform. It employs AXI, AHB, and APB buses for communication and high-performance custom IP components designed by ITRI (PACDSPs, EMDMA, and DDR2 controller), connected to the AXI bus to accelerate multimedia applications, such as H.264 video codec. Standard IP components including ARM, SDRAM, DMA, SRAM, Ethernet and LCD are connected to the AHB bus for normal applications. Finally, low-frequency IP blocks such as UART, Timer, I2S, I2C, and watchdog are connected to the APB bus.
Figure 1. ITRI's Android-compatible multimedia SOC platform.
This case study describes the joint effort by ITRI and SpringSoft engineers to address the verification challenges presented by ITRI SOC design using the SpringSoft ProtoLink Probe Visualizer. The problem encountered is related to the audio function, which worked well (can record and play) in the FPGA prototype board without booting up the OS, but failed if Linux was booted up on the platform.
It is very difficult to debug such a problem in the FPGA prototyping environment with traditional debug methods. Visibility into the FPGA is limited to a few signals and cycles, which does not provide enough information to locate the problem. Alternatively, it is not feasible to troubleshoot the problem with register transfer level (RTL) simulation because it can take an incredible amount of time to boot up the OS (e.g., Linux). Since the problem could be caused by software, hardware or driver, it is also challenging to clarify who should take the responsibility.
A different approach
A more efficient verification methodology was needed to help simplify debug. ITRI was initially concerned that its customized prototype board might not accommodate the interface required by SpringSoft's ProtoLink Probe Visualizer, a new prototype verification environment that uses software-based methods to achieve a high level of design visibility and accelerate debug starting at the RTL design stage all the way through final implementation.
After doing some quick tests, SpringSoft engineers verified that the standard J-connector on the custom ITRI prototype board could be used without problem to bridge the engineering workstation running the Probe Visualizer software to the prototype board. An extra phase lock loop (PLL) was added to the board to provide the required sampling clock. The FPGA setup process was pretty straightforward and easily integrated into existing scripts to automate instrumentation of approximately 100 signal probes, enabling a six-fold increase in visibility compared to previous methods. Because all the probe data was saved on the external 2-GByte Probe memory without using FPGA resources, the overhead of the extra probe logic was only 2% of the FPGA, which is relatively small. The external memory also provided the data capacity needed to save cycles long enough for engineers to clearly understand the relationships between the software, hardware and driver.
The ITRI team proceeded to debug using the probe data with the advanced visualization, tracing and analysis capabilities of SpringSoft's Verdi Automated Debug System. After multiple debug iterations, two issues were found: 1) the USB interrupt locked ARM for a long time so the FIFO in I2S is emptied causing a problem and 2) the priority of Timer interrupt was higher than DMA interrupt and again caused the FIFO in I2S to empty. With the ability to debug in familiar RTL, ITRI engineers were able to analyze design behavior and quickly identify that the root cause of these bugs came from two different scenarios despite the common symptom they presented.
Figure 2. Unintended emptying of a FIFO creates a debug requirement.
As a result, additional critical signals had to be observed but were missing from the original probe list. Using the fast Probe ECO flow, ITRI engineers added 10 new signals in just about 10 minutes without having to recompile the entire design. This was a major time savings compared to the two to three hours required by traditional debug methods to pull the new signals in RTL and then rerun synthesis and place-and-route operations for this particular design.
Engineers were able to simply drag and drop the additional probed signals in RTL from the Verdi debug environment to Probe Visualizer. The system automatically correlated signals from RTL-to-gate level and performed a fast partial routing directly on the FPGA place-and-route files, significantly reducing debug turn-around time and enabling multiple debug sessions in a short time-frame. Even "black box" IP blocks used in the design could be probed by providing only EDIF names.
Assessing the results
After fixing the problems and successfully taping out the design, ITRI engineers reviewed the actual time spent on the project and assessed the results of the new FPGA-based SOC prototype verification methodology.
Roughly two months were spent doing the RTL design, simulation, protocol verification and FPGA implementation. The time spent on driver porting and verification was much shorter at about only two weeks. Engineers then spent another two months attempting to troubleshoot the audio problem using a hardware logic analyzer to check FPGA internal signals and add observation points into the audio driver to correlate and find the problem. This hardware-assisted FPGA debug approach took almost the same amount of time as design development, but with no result, which was quite frustrating for the ITRI team. However, after an initial one-week learning curve and some application training/ support from SpringSoft, ITRI engineers were able to clarify the two issues in just one week using the ProtoLink Probe Visualizer!
Figure 3. IP design, verification and debugging time line.
For ITRI, ProtoLink Probe Visualizer has proven to be a very effective FPGA prototype-debug method. Engineers are no longer limited to conventional debugging methods in software which may cause other problems for real-time applications. By maintaining the original software and watching the real-time RTL behavior of more FPGA signals for millions of cycles, users can gain the visibility needed to better understand and more easily debug design problems.
By Howard Mao
and Vext Chen
Howard Mao is Senior Director of the ProtoLink product line for SpringSoft. Howard holds Masters of Science and Bachelor of Science degrees in Electronic Engineering from National Chiao-Tung University in Hsinchu, Taiwan. He can be reached at firstname.lastname@example.org
Vext Chen is Technical Deputy Manager of the design flow development department for ITRI. Vext holds Masters of Science degree in Electrical Engineering from National Chung-Hsing University in Taichung, Taiwan. He can be reached at email@example.com
Go to the SpringSoft, Inc. website to learn more.