October 27,2011 -- Synthesis and layout tools often make design changes in an attempt to introduce power savings. We are aware of a number of incidents where one of these techniques, namely, the insertion of clock gating cells in the clock network, has corrupted the existing synchronization structures present in the design to avoid clock domain crossing (CDC) issues.

Clock-gating is a very popular technique for power reduction for enable based registers, as described in Figure 1 below.

Figure 1. Enable based Flip-register.

The above figure shows a schematic of an enabled flip-flop. When the EN signal is inactive, the register re-circulates the existing value through the multiplexer at each pulse of the CLK. The re-circulation of the data causes power consumption in the multiplexer and the D flip-flop without any change in the Q signal. If a large number of such registers are present in the design, the power consumption could be large.

The EN of the above schematic can be rewired as shown below in Figure 2 to gate the CLK in order to save power when the EN is inactive.

Figure 2. Clock-gating example.

But this kind of latch-free clock gating requires that enable signal should held constant from the active edge of the clock until the inactive edge of the clock. This is done in order to make the generated clock predictable and glitch free.

To overcome this strict requirement, EN of the above schematic can be rewired using a latch as shown below in Figure 3.

By using this technique, enable (EN) is held stable from the active edge of the clock till the inactive edge arrives, thus satisfying the requirement automatically. Also it is common practice to use an integrated clock-gating (ICG) cell because it will result in better clock tree synthesis and make sure that the latch and the AND gate are not placed far apart.

Figure 3. Clock-gating example.

While clock gating transformations are typically safe and do not affect functionality of the design, they may become harmful and cause chip failure if applied blindly on paths crossing clock domains. Clock-gating transformations during low-power synthesis can break synchronization structures for clock domain crossings and it may happen in different ways. See the below example in Figure 4 illustrating a transformation reported by a customer using a layout tool to save power.

Before the transformation, the structure is a properly synchronized clock domain crossing, where the signal in one domain (Ck1) is properly synchronized using the multi-register scheme in destination domain (Ck2). Since the output of first register in the destination domain (Ck2) is metastable this flip-register output should not be used in the design for any function. But clock gating transformation was not aware of CDC structures and clock gating insertion uses output of first flop in destination domain (Ck2) causing break in functionality, and such a faulty circuit if goes undetected can cause chip failure.

Figure 4. An example of how clock-gating affects metastability.

Preserving synchronization logic during clock gate insertion

Atrenta has developed a flow using SpyGlass CDC to preserve the synchronization logic from being affected during clock-gating insertion later in the flow. In this solution, SpyGlass CDC can be run on multi-clock designs to create a report of the metastable registers. Once this information is available, a script can be run to convert that report to a constraint file. This file contains a list of synchronized and unsynchronized crossings in the design, along with the names of source and destination registers, for use in downstream tools performing power optimization. Using this report you can generate constraints for excluding metastable elements from clock gating. See Figure 5 for an example of an SDC file generated for excluding metastable registers.

Figure 5. Sample SDC file generated for excluding metastable registers.

Impact on power saving

The number of registers on clock domain crossings is typically a small fraction of the total number of registers in a design. Preventing clock gating on such registers should not cause major loss in power savings. However, if significant power can be saved by allowing clock gating on some clock domain crossings, then individual crossings can be reviewed for safe clock gating. For example, in the case of a handshake protocol, it may be safe to clock-gate the "request" signal, assuming that the same "request" is enabling the data capture on all the bits of a data line (which is typically the case) and the other control logic in the "enable cone" is believed to not harm the synchronization through the gated clock.

In summary

SpyGlass CDC can be used to generate a list of registers to be excluded from clock gate insertion to preserve synchronization structures at crossings. This can potentially save last minute silicon re-spins.

By Pankaj Jain, Namit Gupta and Paras Jain

Pankaj Jain is a Project Manager at STMicroelectronics in Noida, India.

Namit Gupta is a Senior Corporate Application Engineer at Atrenta with responsibility for SpyGlass CDC and Advanced Lint. Namit holds a B.Tech. degree in Electronics from Indian Institute of Technology, Delhi. Interest areas are RTL design and verification, clock domain crossing, design constraints and ESL.

Paras Mal Jain is a Senior Engineering Manager at Atrenta India. Paras holds a BE degree in Computer Science from Birla Institute of Technology and Science (BITS), Pilani. Primarily responsible for SpyGlass CDC and Advanced Lint products. Interest areas are clock domain crossing and formal verification.