June 29, 2012 -- At the recent Design Automation Conference (DAC) in San Francisco, visitors to the EVE booth learned how system-on-chip (SOC) emulators have evolved to support the needs of modern SOC realization. Recent advances in the hardware-verification and system-level-integration capabilities of emulation resonated strongly with the DAC audience. One of the most popular topics at our booth was that of power-aware verification in emulation. Verification engineers and project managers from every market segment either had current or anticipated future needs to functionally verify power-gating scenarios at the system level. They wanted to know what verification providers were doing to address this looming problem.
Power gating, also known as power switching, uses a high-threshold sleep transistor to shut off the VDD to a domain when it is not in use. This technique can greatly reduce leakage-power consumption, an increasingly significant factor relative to active or dynamic power as device geometries have shrunk over the years. And as consumers demand both increased functionality and increased battery life in their devices, the number of power-gated domains has increased as well.
The increased prevalence of power gating presents a number of challenges that make emulation a good platform for functional verification. First, power gating generally occurs at the system level, often controlled by the software or by the primary processor in the design. Realistically testing power gating requires the execution of embedded software on the full-chip netlist. At this level, high gate-counts and long software tests — often including the operating system (OS) boot — can easily extend beyond the reach of simulation. SOC emulators offer the capacity and the execution speeds required to test power-gating scenarios in a reasonable time-frame.
Also related to execution speed is the number of power-gating scenarios that need to be verified. Each power domain requires at least two verification scenarios: the power-down scenario, when the domain is switched off; and the power-up scenario, when the domain is switched on again. These scenarios may also have to be tested in a variety of circumstances. As the number of power domains increases, the number of additional test scenarios grows exponentially, adding increased verification-bandwidth pressure. Once again, emulation offers a likely solution, able to execute these system-level scenarios at speeds orders of magnitude faster than simulation.
But some aspects of power gating are also incongruent with emulation. Emulators are designed to accept register-transfer level (RTL) or gate-level code as their input, and these functional netlists abstract out the VDD. In a typical ASIC flow, power domains and the functionality of power gating aren't written into the RTL code; rather, they are defined in separate power-intent files, using the Unified Power Format (UPF) or Common Power Format (CPF). For an emulator to support power gating, it must be able to apply UPF and CPF power intent to an emulated design that has no concept of voltage.
The indeterminate nature of power gating also presents challenges for power-aware verification in emulation. When a power domain is switched off, and then turned back on again, the state of the memories and registers with that domain are unknown. In simulation, this can be represented as an "x," and x-propagation helps in tracing potential issues in the power-gating functionality. But in the real hardware and in emulation, the state of any individual register or memory location will actually be a one or a zero. While emulation may technically provide a more true-to-life result than simulation, it may also be one that is harder to debug. Successful implementation of power gating in emulation must also include a robust debugging methodology.
When emulators such as EVE's ZeBu compile power-gating functionality into the emulated design, they provide multiple options regarding the values applied to each power domain. When the domain is powered down during run-time, all zeros, all ones, or pseudo-random values can be applied to the registers and memory contents. Applying seed-based pseudo-random values enables more realistic verification, and is fully repeatable, allowing for consistent testing. Combined with scalable closed-loop hardware-debugging capabilities to trace failures in billion-gate, billion-cycle verification, emulation is now poised to offer practical solutions for system-level, power-aware verification.
The emergence of this technology comes none too soon, as it was clear at DAC that power-aware verification is a growing problem that needs a solution — and that the verification community is expecting that solution to come from emulation. Visitors to the EVE booth were eager to view power-related demonstrations, and to discuss their upcoming power-aware verification needs. Simply stated — power is on everybody's mind.
By Lauro Rizzatti
Lauro Rizzatti is General Manager of EVE-USA. He has more than 30 years of experience in EDA and ATE, where he held responsibilities in top management, product marketing, technical marketing and engineering.
Go to the Emulation and Verification Engineering (EVE) website to learn more.