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Gabe Moretti Gabe on EDA Formal Verification and Validation Today one does not hear much about formal verification as a separate technology. It has matured and found its own position within the verification market. There are still a few companies that specialize in formal technology, but with the passing of time they are becoming identified within the verification market. Formal tools are no longer talked about separately, as requiring additional expertise. They are part of both development and verification methods, they are accepted just as logic simulation is accepted. The products are user friendly, follow hardware development methodology, and are well integrated in the design and verification flows. ... read more.

Top 10 Tips for Successful Use of Formal Analysis Involve designers in property specification and, whenever possible, in formal analysis. Apply formal analysis early in the project so that engineers specifying properties see an immediate pay-off. Leverage all forms of automatic assertions, from basic design checkers through assertion synthesis. Leverage assertion-based IP (ABVIP) for standard protocols, especially for on-chip buses. Leverage formal "apps" such as connectivity checking for highly multiplexed SOC pins. Recognize the value of formal analysis for both proving assertions and finding design and specification bugs. Use formal analysis to improve simulation-coverage results by checking for unreachable coverage. Use formal analysis to help with coverage convergence by showing how to hit tough coverage. Recognize the value of "dual-engine" formal analysis and simulation working together on assertions and coverage. Use formal analysis to track down the source of post-silicon bugs whose effects can be captured with assertions. By Thomas Anderson, currently Vice President of Marketing at Breker Verification, and Joseph Hupcey III, Director of Product Management, Functional Verification, Silicon Realization at Cadence Design Systems. These "Top 10 Tips" were discussed in detail in a 3-part series originally appearing in EE Times' EDA DesignLine.

Simulation Coverage and Formal Verification: Unlikely Collaborators?

Closing the coverage gap has been a long-standing challenge in simulation-based verification. Formal verification set-up methodologies lack completion measures like coverage on the simulation side. This article articulates a methodology that uses formal tools to automate coverage closure and specifies coverage as the completion measure for formal verification set-ups.

Read the entire article by Synopsys, Inc. on SOCcentral.

Understanding Formal Verification Concepts-Part 1

This article describes formal verification concepts and the differences between formal and simulation techniques, especially in the context of assertion-based verification. The assertion- based verification flow and some of the formal verification algorithms are also discussed in detail. Last but not the least, a few applications of formal technology in the context of ASIC designs are also presented.

Read the entire article by Atrenta, Inc. on SOCcentral.

Understanding Formal Verification Concepts-Part 2

In this second article in a three-part series about formal-verification concepts, we examine the assertion-based verification flow and some of the formal-verification algorithms. This kind of approach has become necessary as SOC designs become more challenging and as the traditional method of simulation proves too slow, too costly, and insufficient in terms of coverage.

Read the entire article by Atrenta, Inc. on SOCcentral.

Understanding Formal Verification Concepts-Part 3

In this final article in a three-part series about formal verification concepts, we examine the assertion-based verification flow and some of the formal verification algorithms. This kind of approach has become necessary as SOC designs become more challenging and the traditional method of simulation proves too slow, too costly, and insufficient in terms of coverage.

Read the entire article by Atrenta, Inc. on SOCcentral.

Seven Habits of Effective Formal Verification Planning

"Those who fail to plan, plan to fail." This is certainly true when it comes to successful verification, where experience repeatedly demonstrates that success depends on methodical verification planning combined with systematic verification processes.

Read the entire article by Mentor Graphics Corp. on SOCcentral.

Formal Verification Works Well for Connectivity Checking

Connectivity checking — the verification of device wiring — is among the many unheralded, yet essential, tasks in ASIC design. In a nutshell, it's making sure that the connections between blocks of logic are correct. This is not a trivial undertaking as such connections can easily number in the thousands. Certainly this is true for the at ST-Ericsson, where until recently, engineers designing high-performance LTE modems approached this problem via simulation. Last year, however, I worked with a group of them based in Sweden on a pilot project to do connectivity checking using formal-verification techniques. The results, which were a dramatic reduction in the time to coverage closure, are sparking more interest in formal techniques at the company.

Read the entire article by Mentor Graphics Corp. on SOCcentral.

Streamlined Verification Plans Using the Metric Driven Verification Flow

A streamlined verification-planning processes is required to meet today's quality and productivity expectations. The Metric Driven Verification (MDV) flow introduced by Cadence provides many enablers to achieve these goals. The MDV flow starts by creating an executable verification plan, namely the vPlan, using a tool feature called Enterprise Planner which is then read into the Cadence Incisive Enterprise Manager tool, along with the coverage results. This article gives the guidelines in creating a verification plan using the vPlan. It explains a complete verification flow starting from verification strategy planning to closure.

Read the entire article by Cadence Design Systems, Inc. on SOCcentral.

Using Formal Technology to Improve Coverage Results

Debugging continues to be one of the biggest bottlenecks in today's design flow. Debugging touches all processes within a design flow, including the painful task of coverage closure. In this article we explore the debugging aspect of coverage closure, with a focus on the unique ability of formal technology to automatically generate simulation-exclusion files to improve coverage results while reducing the amount of time wasted trying to hit unreachable states.

Read the entire article by Mentor Graphics Corp. on SOCcentral.