Featured Articles

EDA Tools Aim at Improving Yield

With each new process node, additional defect mechanisms appear and hinder the ability to achieve desired yield. The trend toward declining yields has created resurgence in the application of design for manufacturing (DFM) methodologies. Much of this reinvigorated effort relies heavily on a new breed of tools and technologies destined for the designer's hands.

But before designers adopt a comprehensive DFM methodology, it is important to understand the primary types of yield loss. These include 'random' (typically associated with particle defects), 'systematic' (induced by the process or lithography applications) and 'parametric' (which cause timing or other failures as a result of device physics and interconnect effects).

Read the entire article by Mentor Graphics Corp. on SOCcentral.

Comprehensive Characterization Analysis Ensures Fast Yield Ramps

As the semiconductor market shifts to 90nm and lower process technologies, the interactions between design and process are becoming more unpredictable and problematic. Limited visibility into the effects of these interactions on manufacturability, performance and reliability exposes semiconductor vendors to costly yield issues during production which can dramatically impact product margins and delivery schedules.

To manage this risk and to ensure predictable and fast yield ramps, semiconductor companies conduct Product Characterization to determine whether a product is ready for volume production. As part of the overall product characterization process, the product engineer devises a design of experiment (DOE) in which material is produced across the range of the possible manufacturing conditions and tested across the range of the possible operating conditions. The output of this DOE is a wealth of characterization data. The value of the DOE is realized only upon proper and thorough analysis of the data.

Read the entire article by LogicVision, Inc. on SOCcentral.

Improving Test Through Real-Time Information

All of us in the semiconductor test business know the issues: cost of test is too high, quality standards are being raised, parts are more complex, storage of excessive test data is overflowing our networks and data warehouses, and finger pointing continues between ATE vendors, test floor operations, test and product engineering, and the foundries.

Semiconductor test remains primitive compared to the fabrication of the silicon as little investment has been made in changing historic approaches to the business. Cost of test continues to increase. Over the past ten years, significant progress has been made in the fabs by installing process monitoring and optimization methods. Instead of waiting for equipment to break and processes to go out of control, continuous monitoring against statistical guidelines help to keep the multi-billion dollar fabs running with high efficiency.

Read the entire article by Pintail Technologies, Inc. on SOCcentral.