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 Category: Special Topics: Design for Manufacturing: Thursday, September 09, 2010
 Design for Manufacturing

Featured Articles

EDA Tools Aim at Improving Yield

With each new process node, additional defect mechanisms appear and hinder the ability to achieve desired yield. The trend toward declining yields has created resurgence in the application of design for manufacturing (DFM) methodologies. Much of this reinvigorated effort relies heavily on a new breed of tools and technologies destined for the designer's hands.

But before designers adopt a comprehensive DFM methodology, it is important to understand the primary types of yield loss. These include 'random' (typically associated with particle defects), 'systematic' (induced by the process or lithography applications) and 'parametric' (which cause timing or other failures as a result of device physics and interconnect effects).

Read the entire article by Mentor Graphics Corp. on SOCcentral.

Comprehensive Characterization Analysis Ensures Fast Yield Ramps

As the semiconductor market shifts to 90nm and lower process technologies, the interactions between design and process are becoming more unpredictable and problematic. Limited visibility into the effects of these interactions on manufacturability, performance and reliability exposes semiconductor vendors to costly yield issues during production which can dramatically impact product margins and delivery schedules.

To manage this risk and to ensure predictable and fast yield ramps, semiconductor companies conduct Product Characterization to determine whether a product is ready for volume production. As part of the overall product characterization process, the product engineer devises a design of experiment (DOE) in which material is produced across the range of the possible manufacturing conditions and tested across the range of the possible operating conditions. The output of this DOE is a wealth of characterization data. The value of the DOE is realized only upon proper and thorough analysis of the data.

Read the entire article by LogicVision, Inc. on SOCcentral.

Improving Test Through Real-Time Information

All of us in the semiconductor test business know the issues: cost of test is too high, quality standards are being raised, parts are more complex, storage of excessive test data is overflowing our networks and data warehouses, and finger pointing continues between ATE vendors, test floor operations, test and product engineering, and the foundries.

Semiconductor test remains primitive compared to the fabrication of the silicon as little investment has been made in changing historic approaches to the business. Cost of test continues to increase. Over the past ten years, significant progress has been made in the fabs by installing process monitoring and optimization methods. Instead of waiting for equipment to break and processes to go out of control, continuous monitoring against statistical guidelines help to keep the multi-billion dollar fabs running with high efficiency.

Read the entire article by Pintail Technologies, Inc. on SOCcentral.

Designer's Mall

SOCcentral news items about Design for Manufacturing

Magma Design Automation Joins Si2's DFM Coalition (8/25/2010)
Mentor Graphics Provides Comprehensive Verification Support in TSMC AMS Reference Flow 1.0 (6/17/2010)
Cadence Delivers TLM-Driven Design and Verification, 3D-IC Design and Integrated DFM Capabilities to TSMC Reference Flow 11.0 (6/14/2010)
Magma's Talus IC Implementation System Supports TSMC 28-nm Process Technology Through Reference Flow 11.0 (6/11/2010)
TSMC Selects Solido for Variation-Aware Custom IC Design In Analog/ Mixed-Signal Reference Flow 1.0 (6/11/2010)
Mentor Graphics Announces Calibre xACT 3D for Fast and Accurate Extraction Using 3D Field Solver Technology (6/8/2010)
Si2 to Host "Design for Manufacturability Coalition Workshop" at DAC 2010 (5/28/2010)
Valor Releases Major New Functionality In the vSure DFM Product (5/19/2010)
Mentor Graphics Calibre InRoute Delivers True Manufacturing Sign-Off During Physical Design Closure (5/3/2010)
SMIC Bases DFM Sign-Off Strategy on Mentor Graphics Calibre Platform (3/30/2010)
Mentor Graphics Calibre LFD Certifications at TSMC Now Include 28-nm Process Node with TSMC UDFM Engine (3/23/2010)
Mentor Graphics Acquires Valor Computerized Systems (3/18/2010)
PDF Solutions Expands Use of Magma's Quartz Products to Physically Verify CV Test Chips (2/25/2010)
PDF Solutions Selects Magma's Titan to Improve Time-to-Yield of Mixed-Signal SOCs (2/25/2010)
Cadence EDI System 9.1 Addresses Productivity Crisis for Complex SOC Design (2/2/2010)
Berkeley Design and Solido Design Accelerate Nanometer IC-Variation Analysis (1/27/2010)
NEC Electronics Adopts Cadence Encounter Digital Implementation System for 40-nm ASIC Designs (1/25/2010)
Solido Opens Spice-based Variation Designer Platform for Additional Third-party Integration (1/19/2010)
Freescale Collaborates with Mentor Graphics on Tessent Silicon Test, Yield Analysis, Calibre Physical Verification and DFM (1/11/2010)
New Mentor Graphics Tessent YieldInsight Product Improves IC Yield Through Statistical Analysis of Test Failure Data (11/2/2009)
NVIDIA Adopts Synopsys Yield Explorer to Reduce Time-to-Volume (10/29/2009)
SMIC Adopts Cadence DFM Solutions for 65- and 45-nm IP Library Development and Full Chip Production (10/19/2009)
SHHIC Adopts Cadence Solutions for Advanced Semiconductor Design (10/14/2009)

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Magazine & Journal articles on Design for Manufacturing

Seeing Is Believing: How Visualization Simplifies IC DRC SOCcentral (9/1/2010)
Parametric Yield Estimation for SRAM Cells: Concepts, Algorithms and Challenges DAC Knowledge Center (6/17/2010)
The New Standard for 32-nm IC Physical Design and Signoff SOCcentral (3/11/2010)
Design for Diagnosis to Improve IC Yield EDA DesignLine (1/25/2010)
In-Design Metal-Fill Key to Physical-Verification Turn-Around Time for Advanced IC Designs EDA DesignLine (12/8/2009)
Probabilistic Timing Analysis SOCcentral (10/31/2009)
DFM-Compliant IP: Why You Need It, How You Get It SOCcentral (9/9/2009)
Analog and Mixed-Signal IC Debug SOCcentral (8/2/2009)
Design for Manufacturing Sheds the Hype Electronic Design Magazine (6/11/2009)
Manufacturing Compliance: It’s Your Job Printed Circuit Design & Fab (3/1/2009)
Challenges in 45-nm Physical Design SOCcentral (11/6/2008)
Tips to Improve Manufacturability Printed Circuit Design & Fab (11/1/2008)
How Equation-Based DRC Solves Design/ Manufacturing Challenges SCDsource (9/16/2008)
… But Will It Work? SOCcentral (9/2/2008)
A Comprehensive Approach to Manufacturing Variability SOCcentral (9/2/2008)
Manufacturing Concerns Move Up the Design Cycle SOCcentral (9/2/2008)
Solving the DFM Interoperability Crisis SOCcentral (9/2/2008)
Systematic Yield Improvement Using BIST SOCcentral (9/2/2008)
The Shifting Landscape of DFM SOCcentral (9/2/2008)
Migration of the Cell Broadband Engine to 45-nm SOI EDA Tech Forum (6/1/2008)
Improving Fabrication Yields By Design Printed Circuit Design & Fab (4/1/2008)
Probabilistic Approach Helps Ensure DFM Success SCDsource (1/30/2008)
Achieving Yield in the Nanometer Age EDA DesignLine (12/17/2007)
Using DFM Routing to Impact Design Performance and Yield EDA DesignLine (12/4/2007)
Applying Volume Diagnostics to Accelerate Yield Learning SOCcentral (11/5/2007)
Sign-Off for Manufacturability EDA DesignLine (10/8/2007)
How Low Can You Go? A Look at 45-nm IC Design Challenges EDN Magazine (9/13/2007)
Process Intelligent Modeling and Statistical STA improve DFM EDA DesignLine (9/11/2007)
Design For Manufacturing: Still not Ready for Prime Time? Electronic Design Magazine (8/16/2007)
Silicon Validation via LFD Simulation SOCcentral (8/6/2007)
In the Eye of the DFM/DFY Storm EDA DesignLine (5/25/2007)
Measuring Scan Compression Performance EDA DesignLine (5/21/2007)
Model-Based Metal Fill Optimizes Planarization and Increases Yield EDA DesignLine (3/22/2007)
Design for Variability: Design, Process, and Manufacturing Variations in Physical Design EDA DesignLine (3/19/2007)
Test Data Provides Yield Improvement Metrics EDA DesignLine (1/22/2007)
Using Fill Synthesis for Enhanced Planarization - Part 2 EDA DesignLine (11/30/2006)
Using Fill Synthesis for Enhanced Planarization - Part 1 EDA DesignLine (11/27/2006)
Sifting the DFM Players EDN Magazine (8/17/2006)
DFM at DAC SOCcentral (7/14/2006)
Is Chip Design Different After 90nm? EDN Magazine (7/6/2006)
Critical Area: A Metric for Yield Optimizations in Physical Design SOCcentral (6/5/2006)
Strategies to Prevent IC Failures in Volume Production SOCcentral (5/18/2006)
Critical Area Optimizations Improve IC Yields eeDesign (EE Times EDA News) (1/9/2006)
Yield Challenges Require New DFM Approach eeDesign (EE Times EDA News) (11/21/2005)
Managing Variations in IC Physical Design eeDesign (EE Times EDA News) (10/24/2005)
It’s All About the Routing, Stupid! SOCcentral (10/17/2005)
Test Takes New Role in Yield Improvement eeDesign (EE Times EDA News) (10/17/2005)
The Truth About Design for Manufacturing Electronic Design Magazine (9/29/2005)
DFM: What Do the Letters Really Mean? SOCcentral (7/22/2005)
EDA Can't Afford to Ignore Test Chips Any Longer Electronic Design Magazine (7/15/2005)
Improving Yield in RTL-to-GDSII Flows eeDesign (EE Times EDA News) (7/11/2005)
Comprehensive Characterization Analysis Ensures Fast Yield Ramps SOCcentral (7/1/2005)
EDA Tools Aim at Improving Yield SOCcentral (7/1/2005)
Improving Test Through Real-Time Information SOCcentral (7/1/2005)
Model-Based Approach Allows Design for Yield eeDesign (EE Times EDA News) (4/18/2005)
What Designers Need to Know About TCAD eeDesign (EE Times EDA News) (4/4/2005)
Take Designs from Algorithms to Artwork Chip Design Magazine (3/1/2005)
Nanometer Yield Enhancement Begins in the Design Phase Electronic Design Magazine (1/20/2005)
How Statistical Sensitivity Makes Designs Manufacturable eeDesign (EE Times EDA News) (12/9/2004)
Design for Volume Chip Design Magazine (11/1/2004)
Accelerating SOC Design While Reducing Costs SOCcentral (10/25/2004)
Mano a Mano with Manufacturing EDN Magazine (10/25/2004)
How Diagnostics Accelerate Nanometer Yield Ramp eeDesign (EE Times EDA News) (10/1/2004)
Manufacturing-Aware Design Helps Boost IC Yield eeDesign (EE Times EDA News) (9/9/2004)
Improving Yields without Compromising Area eeDesign (EE Times EDA News) (8/13/2004)
If You Can't Build It, It Isn't Worth Much EDN Magazine (4/1/2004)
Design-for-Manufacturing Demands New Infrastructure Electronic Engineering Times (EE Times) (1/15/2004)
How Designers Can Increase Parametric Yield eeDesign (EE Times EDA News) (11/21/2003)

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Tutorials, White Papers & Conference Papers on Design for Manufacturing

A Methodology to Improve Timing Yield in the Presence of Process Variations Design Automation Conference (DAC)
Accelerating Nanometer Yield Ramp with Yield Diagnostics Cadence Design Systems, Inc.
An Effective DFM Strategy Requires Accurate Process and IP Pre-Characterization Design Automation Conference (DAC)
An IC Manufacturing Yield Model Considering Intra-Die Variations Design Automation Conference (DAC)
An Up-stream Design Auto-fix Flow for Manufacturability Enhancement Design Automation Conference (DAC)
Are There Economic Benefits in DFM? Design Automation Conference (DAC)
BEOL Variabiity and Impact on RC Extraction Design Automation Conference (DAC)
Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting (14.4) Design Automation Conference (DAC)
CAD Tools for Variation Tolerance Design Automation Conference (DAC)
Characterization-to-Silicon DFM Design Flow Magma Design Automation, Inc.
Cognitive Radio Techniques for Wide Area Networks Design Automation Conference (DAC)
Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits (50.1) Design Automation Conference (DAC)
Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks (19.2) Design Automation Conference (DAC)
Extraction of Statistical Timing Profiles Using Test Data (29.3) Design Automation Conference (DAC)
Fast Min-Cost Buffer Insertion under Process Variations (19.1) Design Automation Conference (DAC)
Line End Shortening is not Always a Failure (15.5) Design Automation Conference (DAC)
Modeling Litho-Constrained Design Layout (19.4) Design Automation Conference (DAC)
Modeling of Intra-Die Process Variations for Accurate Analysis and Optimization of Nano-scale Circuits Design Automation Conference (DAC)
Novel Sizing Algorithm for Yield Improvement under Process Variation in Nanometer Technology Design Automation Conference (DAC)
On the Need for Statistical Timing Analysis Design Automation Conference (DAC)
OPC-Free and Minimally Irregular IC Design Style (51.2) Design Automation Conference (DAC)
Optical Proximity Correction (OPC)-Friendly Maze Routing Design Automation Conference (DAC)
Overcoming the Challenges of Design Verification and Hardware Validation Kozio, Inc.
PANEL: DFM: Where's the Proof of Value? Design Automation Conference (DAC)
PANEL: How Will the Fabless Model Survive? (01.1) Design Automation Conference (DAC)
Parametric Yield Estimation Considering Leakage Variability Design Automation Conference (DAC)
Performance-Impact Limited Area Fill Synthesis Design Automation Conference (DAC)
Phase Correct Routing for Alternating Phase Shift Masks Design Automation Conference (DAC)
Power Grid Verification, Cadence Design Systems, Inc.
Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools Design Automation Conference (DAC)
Process Variation Aware OPC with Variational Lithography Modeling Design Automation Conference (DAC)
RADAR: RET-Aware Detailed Routing Using Fast Lithography Simulations Design Automation Conference (DAC)
Requirements for True DFM and DFY Magma Design Automation, Inc.
Routing Architecture Exploration for Regular Fabrics Design Automation Conference (DAC)
Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Control Design Automation Conference (DAC)
STAC: Statistical Timing Analysis with Correlation Design Automation Conference (DAC)
Standard Cell Characterization Considering Lithography Induced Variations Design Automation Conference (DAC)
Statistical Gate Delay Model Considering Multiple Input Switching Design Automation Conference (DAC)
The DFM Pandemic: How Many Chips Have to Die? Pyxis Technology, Inc.
The Embedded Path to Low Defects per Million and Fast Silicon Bring-Up LogicVision, Inc.
Toward a Methodology for Manufacturability Driven Design Rule Exploration Design Automation Conference (DAC)
Toward a Systematic-Variation Aware Timing Methodology Design Automation Conference (DAC)
Understanding Design for Yield Ponte Solutions, Inc.
Variability Driven Gate Sizing for Binning Yield Optimization Design Automation Conference (DAC)
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop (50.2) Design Automation Conference (DAC)
Variation-Tolerant Circuits: Circuit Solutions and Techniques Design Automation Conference (DAC)
We Haven’t Survived 65nm: We’re Just in the Eye of the Storm! Pyxis Technology, Inc.
WIP Tracking IC Manufacturing Workflow and Cycle-time Reduction eSilicon Corp.

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