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FPGA Design Meets the Heisenberg Uncertainty Principle
The classic dilemma of meeting design specifications - on schedule - with increasingly complex devices is now a harsh reality for FPGA designers. Clearly, it has become more challenging to converge on these requirements in terms of both performance and area utilization in high-end FPGA designs. To complicate matters, last-minute design functionality changes after assumed project "completion" have also become more common. One well known company literally wasted months trying to incorporate a single late-coming engineering change order (ECO), because the design team encountered difficulties maintaining the previous timing results after making this specification change. It's like the Heisenberg Uncertainty Principle wreaking havoc in the programmable logic realm!
To eliminate the uncertainties now governing FPGA-based projects, companies must adopt a complete design methodology that provides the right combination of automated and interactive optimizations via logical and physical synthesis techniques, along with the right mix of analysis, debug and ECO capabilities. This powerful combination of user control and flexibility is the only proven route to predictable, accurate and ultimately successful design of leading-edge FPGAs today.
Read the entire article by Mentor Graphics Corp. on SOCcentral.
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