Featured Articles

FPGA Design Meets the Heisenberg Uncertainty Principle

The classic dilemma of meeting design specifications - on schedule - with increasingly complex devices is now a harsh reality for FPGA designers. Clearly, it has become more challenging to converge on these requirements in terms of both performance and area utilization in high-end FPGA designs. To complicate matters, last-minute design functionality changes after assumed project "completion" have also become more common. One well known company literally wasted months trying to incorporate a single late-coming engineering change order (ECO), because the design team encountered difficulties maintaining the previous timing results after making this specification change. It's like the Heisenberg Uncertainty Principle wreaking havoc in the programmable logic realm!

To eliminate the uncertainties now governing FPGA-based projects, companies must adopt a complete design methodology that provides the right combination of automated and interactive optimizations via logical and physical synthesis techniques, along with the right mix of analysis, debug and ECO capabilities. This powerful combination of user control and flexibility is the only proven route to predictable, accurate and ultimately successful design of leading-edge FPGAs today.

Read the entire Mentor Graphics Corp. article on SOCcentral.

Logic and Physical Synthesis: Should There Be a Difference?

Of course, there is a difference between logic synthesis and physical synthesis. Typically, the former maps an RTL description to a set of gates to realize the same functionality. Conversely, the latter implements the netlist on a given (minimal) floorplan and maintains or improves the quality of physical characteristics of the design. These characteristics could include timing, power, testability, signal integrity, routability and manufacturability, all leading to improved yield for the device.

Looking through the reality viewfinder, however, shows a much different perspective for many design project teams. For example, logic synthesis is a disparate step, performed in almost complete isolation. The logic design engineer writes (or receives) functionally verified RTL code and begins to synthesize it with incomplete timing constraints. Whether the concept of wireload is used for selecting the most optimal cells, traditional methods ignore a design’s physical requirements. This leads to a false sense of "timing closure" too early in the design process and a false sense of confidence that the logical netlist can be implemented by the physical design team.

Read the entire Magma Design Automation, Inc. article on SOCcentral.

The Evolution of FPGA Physical Synthesis

The emergence of fast and complex FPGA devices has, like in the ASIC world, created the need for considering physical characteristics of a design during synthesis in order to avoid costly, time-consuming design iterations. A few EDA vendors are attempting to tackle this issue by applying FPGA physical synthesis approaches derived from the historical evolution of ASIC logic synthesis. However, when engineers need to employ physical optimizations on FPGAs they cannot use the same tools that are used to perform the function in ASIC design, because the silicon fabric is totally different. In the ASIC methodology engineers control the placement of a logic cell and, by following the foundry design rules, generate the connectivity path between the pins of the cells. An FPGA has a rigid fabric: the connectivity grid is fixed once the cell is placed. Therefore a physical synthesis tool must have intimate knowledge of the device fabric including the complex routing structures in order to most efficiently create placement and perform netlist optimizations based upon physical design information.

Read the entire Synplicity, Inc. article on SOCcentral.

Graph-Based Physical Synthesis for FPGAs

Traditional synthesis technology is failing to address the needs of today’s extremely large and complex FPGA designs implemented in devices at the 90nm technology node and below. Conventional FPGA synthesis engines are based on ASIC-derived techniques such as floorplanning, in-place optimization (IPO), and – more recently – physically aware synthesis. However, these ASIC-derived synthesis algorithms are not appropriate for use with the regular architectures and pre-defined routing resources presented by FPGAs. The end result is that all traditional FPGA synthesis approaches require multiple time-consuming iterations between front-end synthesis and downstream place-and-route tools so as to achieve convergence and timing closure.

Read the entire Synplicity, Inc. article on SOCcentral.