Page loading . . .

 Category: Vendor Webcasts: Upcoming Webcasts: Wednesday, October 07, 2015
Frequency Synthesis-Part 2: Direct Digital Synthesis (DDS)   Featured
Sponsor: Analog Devices, Inc. (ADI)
Webcaster: EE Times Education & Training
 Printer friendly
 E-Mail Item URL

April 11, 2012 -- This webinar concludes a two-part series on frequency synthesis, with an introduction to direct digital synthesis. We give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We also discuss the trade-offs between PLL and DDS technology as a base choice for frequency synthesis needs.

Go directly to the EE Times Education & Training webcast site to view this presentation. Registration may be required.

Keywords: embedded system design, embedded systems, DSP, digital signal processing, digital signal processors, direct digital synthesis, phase-locked loops, PLLs, Analog Devices, Inc. (ADI), EE Times Education & Training
336/37982 4/11/2012 954 116
Designer's Mall

 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
and receive news, article, whitepaper, and product updates bi-weekly.


Verification Contortions

Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Real Talk

Drilling Down on the Internet of Things

Ramesh Dewangan
VP Product Strategy
Real Intent, Inc.

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
DSP Design
Analog Design
Digital Design
Mixed-Signal Design
RF Design
EDA Tool Development

IC Packaging
PCB Design
RTOS Development
RTL Design
SystemC Design
SystemVerilog Design
Verilog Design
VHDL Design

Post a Job
Only $100 for 30 days

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts


Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
258.548  0.0625