Page loading . . .

  
 Category: Vendor Webcasts: Upcoming Webcasts: Thursday, November 27, 2014
Frequency Synthesis-Part 2: Direct Digital Synthesis (DDS)   Featured
Sponsor: Analog Devices, Inc. (ADI)
Webcaster: EE Times Education & Training
 Printer friendly
 E-Mail Item URL

April 11, 2012 -- This webinar concludes a two-part series on frequency synthesis, with an introduction to direct digital synthesis. We give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We also discuss the trade-offs between PLL and DDS technology as a base choice for frequency synthesis needs.

Go directly to the EE Times Education & Training webcast site to view this presentation. Registration may be required.

Keywords: embedded system design, embedded systems, DSP, digital signal processing, digital signal processors, direct digital synthesis, phase-locked loops, PLLs, Analog Devices, Inc. (ADI), EE Times Education & Training
336/37982 4/11/2012 864 97
Designer's Mall

0



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Executive
Viewpoint

Verification Contortions


Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Executive
Viewpoint

Deep Semantic and Formal Analysis


Dr. Pranav Ashar
CTO, Real Intent

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts
Newsletters



About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
258.548  0.0625