April 24, 2012 -- Clock jitter is probably the most obscure specification in data converters. Clock jitter creates uncertainty around the moment when an analog-to-digital converter (ADC) samples the signal. It also adds to conversion noise, and the combination reduces overall system performance. As data converters have evolved to ever-higher sampling frequencies and higher resolutions, they become more sensitive to external conditions, including clock timing quality. Therefore, clocks must be treated as delicate analog signals requiring minimal disturbances.
This webinar will focus on:
Analyzing the effect of jitter on the data converters' sampling error using the frequency domain and the corresponding phase noise representation of jitter.
Analyzing the jitter characteristics of oscillators and phase locked loops (PLLs), which are the most common clock sources in the system.
Reviewing wireless communications application examples to illustrate the sampling error mechanisms and their impact on the performance of the ADCs.
Presenting typical jitter self-referenced measurements and analyzing their relationships to jitter.
Understanding frequency domain mechanisms that relate jitter to sampling errors enables designers to handle the design trade-offs and to achieve optimal system and data converter performance.
Go directly to the EE Times Education & Training webcast site to view this presentation. Registration may be required.
Keywords: computer system design, general-purpose computers, special-purpose computers,
analog-to-digital converters, A-D converters, ADCs, EDA, EDA tools, electronic design automation, jitter, signal integrity, noise, Synopsys, EE Times Education & Training
336/38185 4/24/2012 660 131
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