April 26, 2012 -- The trend towards internet-connected consumer devices is driving an increase in the audio requirements and complexity of today's SOCs. Designers are turning to dedicated audio subsystems to off-load the audio processing from the host processor, thus reducing design complexity and improving the performance and efficiency of the SOC.
This webinar will focus on:
The growing complexity of audio requirements for advanced SOC designs.
How a pre-verified, integrated audio IP subsystem solution, consisting of hardware, software and prototypes reduces integration effort, lowers risk and accelerates time-to-market.
The feature requirements for implementing audio functionality into a SOC.
How configuration of a complete audio IP subsystem can be done in hours.
Go directly to the EE Times Education & Training webcast site to view this presentation. Registration may be required.
Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, audio processing, IP, intellectual property, cores, Synopsys, EE Times Education & Training
336/38243 4/26/2012 629 117
Designer's Mall
0.015625
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