May 1, 2012 -- In this webinar, industry leaders Cadence, TSMC, and ARM outline their visions for 20-nm silicon success and walk you through 20-nm challenges and offer their experiences, guidance, and recommendations to help you gain clarity on how to succeed at advanced-node design. Find out what it takes to enable foundry-optimized, higher-performance, lower-power designs at 20nm.
Go directly to the EE Times Education & Training webcast site to view this presentation. Registration may be required.
Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, IP, intellectual property, cores, Cadence Design Systems, EE Times Education & Training
336/38329 5/1/2012 531 91
Designer's Mall
0.015625
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