Page loading . . .

  
 Category: News: News Archive 2004: Wednesday, June 19, 2013
Mindready Solutions Joins the JTAG Technologies Third-Party Applications Program  
 Printer friendly
 E-Mail Item URL

December 20, 2004 -- JTAG Technologies has announced the addition of Mindready Solutions to its Authorized Applications Provider (AAP) program. With the ever increasing number of users of boundary-scan, the demand for consulting services and solutions has soared. The JTAG Technologies AAP program, consisting of a select group of third-party developers of boundary-scan testing and programming applications based on JTAG Technologies products, is an important answer to this need.

Mindready has demonstrated excellent performance in design analysis, test coverage maximization, test program development, and in-system programming based on JTAG Technologies' tools. Mindready is a very valuable addition to the AAP program to work alongside electronics designers and manufacturers, helping them understand the benefits of boundary-scan and assuring rapid realization of these benefits.

Ray Dellecker, North American Manager of Marketing for JTAG Technologies, said, "Mindready adds an important service capability to our lineup of products and services. We are dedicated to helping industry obtain all of boundary-scan's tremendous power, as demonstrated by our new partnership with Mindready."

Go to the JTAG Technologies, Inc. website to find additional information.

E-mail JTAG Technologies, Inc. for more information.

Read more about
JTAG Technologies, Inc.
on SOCcentral.com


Keywords: JTAG Technologies,
550/10692 12/20/2004 3542 315
Designer's Mall
4th Of July countdown banner
0.390625



 Search for:
            Site       Current Category  
   Search Options


Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Reducing Power
by Raising the
Level of Abstraction


David Pursley
Director,
Product Marketing
Forte Design Systems

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Summertime and the Livin' Ain't Easy


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL?


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.550  0.453125