December 21, 2004 -- Synopsys, Inc. announced today that Artisan Components, Inc. has standardized on Synopsys' ESP full-custom memory equivalency checker for its new low-power, high-density Metro Platform memories. ESP's symbolic simulation technology enabled Artisan to verify its memory generators, while realizing a 5X reduction in time-to-results as compared to verification methods that rely on traditional simulation only.
"ESP -- our longstanding choice for memory verification -- gives us fast, comprehensive equivalency checking that enables us to cut our time-to-results from days to hours," said Dhrumil Gandhi, senior vice president of product technology at Artisan. "In order to support leading-edge low-power design techniques, Artisan's Metro memories are significantly more complex. Synopsys' ESP verification solution plays a major role in helping us meet our customers' first-pass silicon requirements."
ESP is a fast, comprehensive memory equivalency checker that addresses the gap in full-custom verification by thoroughly and quickly comparing a Verilog simulation model directly against the corresponding HSPICE netlist. Its patented application of symbolic simulation techniques and formal proof engines removes the RTL restrictions and circuit limitations placed on design teams by traditional logic abstraction methods while its proprietary hierarchical compression technique delivers the increased capacity demanded by today's memory systems.
