March 23, 2004 -- The Fabless Semiconductor Association (FSA) announced today that it has received widespread industry support for the development and future adoption of a method to document the contents of a process design kit (PDK). A PDK is a set of data files that enable analog circuit and layout designers to efficiently design an IC using a set of EDA tools and a selected foundry process.
The FSA’s Mixed-Signal (MS)/RF Foundry Committee’s PDK working group has released its Mixed-Signal/RF PDK Checklist, which provides guidelines to showcase PDK quality. The Checklist describes simulation models, technology files, design rule files and parameterized cell generators used to design today’s complex mixed-signal and RF ICs. Checklists will be delivered with new MS/RF PDKs over the next several months and are targeted to become standard practice by the end of the year.
Companies represented in the Committee’s working group include 1st Silicon, Agilent Technologies, austriamicrosystems, Cadence Design Systems, HPL, Jazz Semiconductor, Mindspeed Technologies, OK Initiative, PolarFab, Silvaco and TSMC. The FSA Mixed-Signal, RF Foundry Committee was founded to accelerate the formation of an advanced mixed-signal/RF foundry supply chain and ecosystem for fabless and hybrid semiconductor companies. The PDK/Roadmap working group was chartered to first develop a format for PDK representation and common terminology for describing MS/RF PDK contents and inputs. Its second goal is to develop PDK quality criteria at critical delivery milestones and streamline the PDK development process.
"The Checklist is the first deliverable from the Mixed-Signal/RF Foundry Committee. It serves as the foundation for this working group to help streamline foundry, customer and supplier processes," said Jodi Shelton, co-founder and executive director of the FSA. "The Checklist showcases best practices in the semiconductor industry and serves as the ingredients list and ‘nutrition facts panel’ for a design kit, and we hope it will become the de facto standard."
The Checklist will be delivered with each release version of an MS/RF PDK developed or co-developed by foundries, EDA tool vendors and design service companies. The Checklist is both foundry and EDA vendor neutral. The easy-to-read two-page document consists of three sections. The foundry document section describes the specific documents, revisions and dates that were used to build the PDK. The EDA tool section describes the software tools, vendors, revisions and release dates used to qualify the PDK. The device section summarizes the symbols, SPICE models, attributes, parameterized cells and verification of each of the devices.
"Analog, mixed-signal and RF designers need to know how much they can trust what is in their PDKs throughout the semiconductor process life cycle," stated Ken Brock, chair of the PDK working group and vice president of marketing at Silvaco. "This document facilitates the clear communication between foundry, fabless customer, EDA vendor, intellectual property (IP) developer and design service providers."
Go to the Fabless Semiconductor Association (FSA) website to find additional information.