July 6, 2004 -- MoSys, Inc. and Open-Silicon, Inc. have announced the licensing of 1T-SRAM-R embedded memory technology to Open-Silicon. The 1T-SRAM-R technology has been proven to dramatically reduce soft error rates (SERs) to fewer than 10 FIT/Mb in 0.13-micron process technology resulting in improved system-level reliability at a low cost while still maintaining the simple, industry-standard SRAM interface.
"MoSys' 1T-SRAM-R memory, including it's patented Transparent Error Correction (TEC) technology, provides a valuable solution for embedding large high-performance, low-power memories cost-effectively into SoC designs," said Rajesh Shah, Director of Engineering and IP at Open-Silicon. "1T-SRAM-R memory technology in collaboration with our OpenMODEL concept addresses designers' growing need to make intelligent and informed choices that lower cost and reduce risk at each step of the ASIC implementation."
Go to the MoSys, Inc. website to find additional information.