| Silvaco Launches Harmony-AMS Analog/Mixed-Signal Simulator |
June 7, 2004 -- Silvaco International has announced the release of Harmony-AMS Analog/Mixed-Signal Simulation Platform built upon simulator technology from Silvaco and its wholly owned subsidiary, Simucad. Harmony-AMS includes the Silos Verilog ... read more |
| Maury Microwave Selects Agilent Technologies' EDA Tools to Streamline RF, Microwave Design Flow |
June 7, 2004 -- Agilent Technologies, Inc. announced that Maury Microwave has adopted Agilent's Advanced Design System (ADS) electronic design automation (EDA) software platform to help streamline its RF and microwave design flow. The multiyear ... read more |
| Cadence Announces First Encounter Global Physical Synthesis |
June 7, 2004 -- Cadence Design Systems, Inc. has announced Cadence First Encounter Global Physical Synthesis (GPS), a new product that integrates silicon virtual prototyping and second-generation global physical synthesis technology into a singl ... read more |
| Jasper Design Automation Secures $13.5 Million in Series C Funding |
June 7, 2004 -- Jasper Design Automation has raised $13.5 million in a Series C round of funding led by Accel Partners. Theresia Gouw Ranzetta, general partner with Accel Partners, will join the board of directors. Together with the two previous ... read more |
| Genesys Testware Introduces Design for Manufacturability Solution for System ICs |
June 7, 2004 -- Genesys Testware, Inc. has announced ChiptestMaker, a Design for Manufacturability (DFM) solution for system IC. ChiptestMaker can be used to increase yield and test coverage while decreasing test time for system IC. ChiptestMake ... read more |
| Denali Joins Synopsys SystemVerilog Catalyst Program |
June 7, 2004 -- Denali Software has joined the Synopsys SystemVerilog Catalyst program. The industry program is designed to speed support of SystemVerilog by electronic design automation (EDA) vendors, verification intellectual property (IP) sup ... read more |
| Cadence and ASML Sign Multi-Year Business Agreement to Develop Advanced DFM Solutions |
June 7, 2004 -- Cadence Design Systems, Inc. and ASML MaskTools, an ASML business unit, today announced a multi-year, multi-million dollar software licensing and joint development agreement for advanced resolution enhancement technology (RET) so ... read more |
| Apache's SkyHawk Removes Guesswork from Power Grid Design in Nanometer Chips |
June 7, 2004 -- Apache Design Solutions, Inc. has announced SkyHawk, a new automated constraint-driven power grid generation and optimization engine for nanometer SOCs. The new product helps chip designers determine power grid requirements early ... read more |
| Agilent Technologies, CST Announce Exclusive Alliance on 3D EM Simulation Technology |
June 7, 2004 -- Agilent Technologies, Inc. and Computer Simulation Technology (CST) have announced an exclusive alliance to bring three-dimensional electromagnetic (EM) technology to a wider range of RF and microwave design engineers. The allian ... read more |
| True Circuits Introduces New Line of Phase-Locked Loop Hard Macros |
June 7, 2004 -- True Circuits, Inc. (TCI) has announced the immediate availability of a new line of Phase-Locked Loop (PLL) hard macros that are one-third the die size of its current standard PLL products.
The die area of these new high-p ... read more |
| CoWare SPW Supports VHDL Users with Integration of Mentor Graphics' ModelSim Simulator |
June 7, 2004 -- CoWare, Inc. has announced support for VHDL co-simulation through the integration of CoWare SPW and Mentor Graphics ModelSim simulator. This integration lets design teams using ModelSim leverage SPW -- a complete platform for the ... read more |
| Aldec Releases Riviera-IPT with Co-Verification support for ARM |
June 7th, 2004 -- Aldec, Inc. has announced the release of Riviera-IPT with support for ARM. This version of Riviera-IPT provides a seamless, high-speed co-verification and debug environment for complex embedded software/hardware co-development ... read more |
| Xilinx Unveils Virtex-4 Family of Multi-Platform FPGAs Featured |
June 7, 2004 -- Xilinx, Inc. unveiled details of itsVirtex-4 Platform FPGAs, the fourth generation Virtex product. Enabled by the Advanced Silicon Modular Block (ASMBL) architecture, the Virtex-4 product line features multiple domain-optimized p ... read more |
| Silvaco International Releases Its Integrated IC CAD Products on Linux and Solaris |
June 7, 2004 -- Silvaco International has announced the release of its integrated IC CAD products -- Gateway Schematic Editor, Expert Layout Editor, Guardian DRC/LVS/LPE -- on Linux and Solaris. This new graphical user interface (GUI) is based ... read more |
| Silvaco Offers Integrated Solution to Nanometer Single Event Effect Failures |
June 7, 2004 -- Silvaco International has announced the release of ATLAS 2/3D Single Event Effects (SEE) Module and the SmartSpice-SEE Module. These have been integrated with the HIPEX Full-Chip Parasitic Extraction tools and HyperFault Mixed- ... read more |
| Celoxica Achieves Automation for SystemC Synthesis |
June 7, 2004 -- Celoxica today announced advanced synthesis technology for the SystemC language. Celoxica's new Agility Compiler synthesizes SystemC directly to high-density FPGA and Programmable SOC logic and generates RTL VHDL and Verilog for ... read more |
| TSMC Selects Atrenta as Reference Flow 5.0 Partner for Power Closure and IC Integration Flows |
June 7, 2004 -- The Taiwan Semiconductor Manufacturing Company (TSMC) has adopted Atrenta’s low power and ERC products as key enabling technologies in the new TSMC Reference Flow 5.0, the industry’s first design flow providing power closure and ... read more |
| TSMC Reference Flow 5.0 is First to Enable Power Closure |
June 7, 2004 -- Taiwan Semiconductor Manufacturing Company (TSMC) has announced Reference Flow 5.0, the first reference flow providing critical power closure and integrated chip-to-package design for nanometer SOC integrated circuits.
Bui ... read more |
| LSI Logic Uses Innovative Landing Zone Approach to Broaden Processor Offering for RapidChip Platform ASIC |
June 7, 2004 -- LSI Logic Corp. has announced two new high-performance industry-standard ARM processor cores available for integration into RapidChip Platform ASIC designs using an innovative and unique Landing Zone region. The proven 200 MHz AR ... read more |
| Analog Devices Releases PLL Circuit Simulation and Evaluation Tool for Phase-Locked Loop Design |
June 7, 2004 -- Analog Devices, Inc. has released ADIsimPLL version 2.5, a comprehensive design and evaluation tool for phase-locked loop (PLL) circuit design. The new ADIsimPLL software tool further removes time-consuming iterations from the de ... read more |
|
