| TSMC and Synopsys Address Design Challenges for 90 Nanometer and Below with TSMC Reference Flow 5.0 |
June 7, 2004 -- Synopsys, Inc. Taiwan Semiconductor Manufacturing Company (TSMC) today announced that TSMC Reference Flow Release 5.0 incorporates features and innovations of Synopsys' Galaxy Design Platform for designs at 130nm, 90nm and below. ... read more |
| Xilinx Acquires Hier Design |
June 7, 2004 -- Xilinx, Inc. today announced the acquisition of privately-held Hier Design, Inc., a pioneer in hierarchical floorplanning and analysis software for high-performance FPGA design.
Hier Design's EDA tools exclusively support X ... read more |
| TSMC and Apache Address Dynamic Power Closure for Nanometer Design |
June 7, 2004 -- Apache Design Solutions today announced that TSMC has adopted RedHawk-SDL as an integral part of its new Reference Flow 5.0 to achieve power closure.
Today's semiconductor devices often contain tens millions of transistors ... read more |
| Toshiba to Start Production of First SoC With the X Architecture |
June 7, 2004 -- The X Initiative, Cadence Design Systems, Inc. and Toshiba Corp. announced that Toshiba has launched the first commercial SOC devices built on the innovative X Architecture design. Toshiba's latest TC90400XBG chip validates the ... read more |
| Teseda Drives DFT Productivity with Teseda WorkBench Software and Teseda V520 Hardware Platform |
June 7, 2004 -- Teseda Corp. has released two new products, the Teseda WorkBench and the Teseda V520 hardware platform. WorkBench is part of the Teseda V500 Design-for-Test (DFT) validation system and the Teseda V520 expands upon the flexibilit ... read more |
| Synopsys Reduces AMBA Bus-Based SoC Design Time with DesignWare Library |
June 7, 2004 -- Synopsys, Inc. announced DesignWare AMBA Connect, a new feature in its DesignWare Library that reduces design time, effort and risk for AMBA bus-based designs. This feature uses Synopsys' coreAssembler tool to automate AMBA desig ... read more |
| Synopsys Delivers Comprehensive Low-Power Solution 2X Power Reduction |
June 7, 2004 -- Synopsys, Inc. announced that Galaxy Power now offers a comprehensive low-power solution for high-performance 90nm designs and that ARM, IBM and NVIDIA have selected Synopsys' Galaxy Power to achieve low-power optimization in the ... read more |
| Synopsys' coreAssembler Tool Decreases Design Time and Reduces SOC Cost |
June 7, 2004 -- Synopsys, Inc. announced the general availability of coreAssembler, a tool that has been used by NEC Electronics and National Semiconductor to implement an intellectual property (IP) based flow, which dramatically reduces design ... read more |
| OEA International Announces New Release of P-GRID Power Distribution Analysis Tool |
June 7, 2004 -- OEA International, Inc. (OEA) has announced a major update to its P-GRID 3.0, a tool for the analysis of complex IC core power distribution networks for excessive voltage drop (IR Drop) and electromigration violations. In today' ... read more |
| Summit to Expand Visual ESC with ARM Models, a New AMBA Bus Model and RealView Debugger Support |
June 7, 2004 -- Summit Design, Inc. has expanded its Visual ESC package with the latest Cycle Callable Models (CCM) for ARM processors, a new AMBA AHB bus model and the ARM RealView debugger. As a part of Summit's Visual Elite functional modelin ... read more |
| Silicon Navigator Licenses Concept Engineering's Schematic Visualization Software |
June 7, 2004 -- Concept Engineering has announced a worldwide OEM license agreement with Silicon Navigator Corp. to bundle Concept Engineering's NlviewQT Widget, a Qt-based visual debugging software engine, into Silicon Navigator's OpenAccess te ... read more |
| Silvaco Delivers Complete IC CAD Tool Flow on Linux and Solaris |
June 7, 2004 -- Silvaco International has announced the release of its integrated IC CAD products -- Gateway Schematic Editor, Expert Layout Editor, Guardian DRC/LVS/LPE on Linux and Solaris. This new graphical user interface (GUI) is based on t ... read more |
| Real Intent's Formal Verification Software Licensed by Sun Microsystems |
June 7, 2004 -- Real Intent, Inc. has announced that Sun Microsystems, Inc. renewed its corporate license for Real Intent's Verix software. Sun selected Verix because of its ability to detect and eliminate classes of design errors early in the d ... read more |
| Prover Technology Adds Support for Equivalence Checking Advanced Synthesis Optimizations to Prover eCheck |
June 7, 2004 -- Prover Technology, Inc. has announced the release of Prover eCheck 4.1, a major update of the this equivalence checker. Prover eCheck 4.1 enables verification of synthesis involving advanced sequential state point optimizations ... read more |
| Powered by Altera Cyclone FPGAs and Nios Processor, KoolSpan Delivers Wi-Fi Network Security |
June 7, 2004 -- KoolSpan, Inc. is using Altera Corp.'s low-cost Cyclone FPGAs and Nios embedded processor to deliver advanced encryption standard (AES) encryption/decryption and other critical functionality in its SecurEdge Lock solution. KoolSp ... read more |
| TSMC and Cadence Tackle Low Power Challenges at 90 Nanometers and below with New TSMC Reference Flow |
June 7, 2004 -- Cadence Design Systems, Inc. has announced the integration of the Cadence Encounter digital IC design platform and the Cadence Allegro system interconnect design platform into TSMC's Reference Flow 5.0. This reference flow includ ... read more |
| Synopsys, ARM Collaborate to Accelerate AMBA AXI Adoption with DesignWare Verification IP |
June 7, 2004 -- Synopsys, Inc. and ARM are collaborating to deliver AMBA AXI verification intellectual property (IP) through Synopsys' DesignWare Library and DesignWare Verification Library. Synopsys and ARM will develop the AMBA AXI verificati ... read more |
| JEDA Technologies Announces PCI-X, SPI-4, Ethernet, ARM AMBA Verification IP |
June 6, 2004 -- JEDA Technologies, Inc. has announced the availability of various Verification IP. The Verification IP's generally referred to as Jeda-Plug-n-Play-Module (JPPM), are built around standard protocols and interfaces commonly used in ... read more |
| eASIC, Golden Gate Technology Announce Adoption of Critical EDA Software to Support Structured ASIC Design |
June 5, 2004 -- eASIC and Golden Gate Technology have announced the adoption of two products from Golden Gate’s GoPower suite. The IC-Plan and PowerPlacer tools will be used for eASIC’s Structured eASIC array. With this cooperation, the partner ... read more |
| Magma and PDF Solutions to Create IC Implementation Flow with Embedded DFM and DFY Capabilities |
June 4, 2004 -- Magma Design Automation, Inc. and PDF Solutions, Inc. have agreed on the preliminary terms whereby the two companies will create the first IC implementation flow with embedded capabilities for design for manufacturability (DFM) a ... read more |
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