Page loading . . .

  
 Category: News: News Archive 2004: Monday, May 20, 2013
Sort Entries by    
Use the input form on the right to search on a word or phrase.  
Page(s): 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 (1181 Entries)
Synopsys Announces National Semiconductor Standardizes on Synopsys VCS, Leda, and Formality 

May 25, 2004 --S ynopsys, Inc. today announced that National Semiconductor Corp. has standardized on the VCS RTL verification solution, the Leda programmable design checker, and the Formality functional equivalence checker. According to Synopsys ... read more

Synopsys Extends VCS With Full-Featured Built-In Testbench Technology 

May 25, 2004 -- Synopsys, Inc. has announced the latest release of the VCS RTL verification solution. VCS, a key component of the Discovery Verification Platform, extends its built-in testbench capabilities to include a set of advanced technolog ... read more

Magma Adopts Legend's MSIM Circuit Simulator for Cell Characterization and Delay Correlation 

May 24, 2004 -- Legend Design Technology Inc. today announced that Magma Design Automation, Inc. has adopted the MSIM circuit simulator for engineering and field support use worldwide after an extensive evaluation.

"The quality of cell mod ... read more

Synopsys Announces Galaxy and Discovery Platform Support for 90 Nanometer IBM and Chartered Processes 

May 24, 2004 -- Synopsys, Inc. has announced validation of the Galaxy Design and Discovery Verification platforms with the 90 nm process platform common to both IBM and Chartered Semiconductor Manufacturing. Using Artisan Components' 90nm SAGE- ... read more

Cadence Delivers 90-nanometer Reference Flow to Optimize Nanometer Design for IBM, Chartered Process Platform 

May 24, 2004 -- Cadence Design Systems, Inc. has announced the availability of a qualified design reference flow validated as compatible with the IBM-Chartered 90-nanometer process platform. The Cadence reference flow seamlessly integrates intel ... read more

UMC 90-nanometer Technology Sees Strong Acceptance from Industry Leaders 

May 24, 2004 -- UMC is driving the foundry industry’s migration to 90nm technology, with some of the world’s largest IC companies currently utilizing UMC for the fabrication of their most advanced 90nm chips. UMC first announced working 90nm cus ... read more

OCP International Partnership Expands Its University Program 

May 24, 2004 -- Open Core Protocol International Partnership (OCP-IP) has announced an expansion of its world-class university program. The expansion incorporates a bibliography of all major papers and sources in the SoC space, listed on the OCP ... read more

Accellera Approves SystemVerilog 3.1a Standard, Begins IEEE Process 

May 24, 2004 -- Accellera today announced that its Board and Technical Committee members -- systems, semiconductor and design tool companies -- have approved SystemVerilog 3.1a as an Accellera standard for language-based design verification, and ... read more

TransEDA Expands the Value of Coverage with New VN-Spec Specification Coverage Tool 

May 24, 2004 -- TransEDA has announced the availability of the company's new VN-Spec Specification Coverage and Impact Analysis Solution. VN-Spec's introduction results from the synergy of TransEDA's coverage products and TNI-Valiosys' technolo ... read more

TransEDA Announces VN-Cover Coverability Analysis Option 

May 24, 2004 -- TransEDA has announced the availability of a Coverability Analysis Option to the company's VN-Cover Coverage Analysis tool. The new Coverability Analysis option to VN-Cover results from the synergy of TransEDA's Coverage Products ... read more

QuickLogic Reference Development Kit Supports New, Low-Power QuickPCI Family 

May 24, 2004 -- QuickLogic Corp. has announced the availability of the PCI-484 Reference Development Kit (RDK) that supports the recently announced, low-power QuickPCI family of devices.

The PCI-484 RDK is an open development platform fo ... read more

Tensilica Announces Design Center Agreement with Genesis Technology 

May 24, 2004 -- Tensilica, Inc. has announced an agreement with Genesis Technology, Inc. (GTI), an independent LSI design company and a large independent semiconductor testing company in Japan. Under this agreement, GTI will become a recommended ... read more

Mentor Graphics Calibre Approved Verification Tool for IBM-Chartered 90nm Design Enablement Platform 

May 24, 2004 -- Mentor Graphics Corp. has announced that its Calibre design-to-silicon platform is an approved physical verification tool for the 90nm semiconductor process platform jointly developed by IBM and Chartered Semiconductor Manufactur ... read more

QuickLogic Reference Development Kit Supports New, Low-Power QuickPCI Family 

May 24, 2004 -- QuickLogic Corp. has announced the availability of the PCI-484 Reference Development Kit (RDK) that supports the recently announced, low-power QuickPCI family of devices.

The PCI-484 RDK is an open development platform fo ... read more

Apache Enhances RedHawk-SDL for Low-Power Designs and Addresses Timing Impact Issues in Nanometer Designs 

May 24, 2004 -- Apache Design Solutions has announced new capabilities in its flagship product, RedHawk-SDL, to address dynamic power integrity issues for advanced low-power designs. The new capabilities also address the critical need to accurat ... read more

Realtek Standardizes Upon the MIPS Architecture for High Performance Broadband SOCs 

May 24, 2004 -- MIPS Technologies, Inc. today announced that Realtek Semiconductor Corp. (Taiwan) has licensed a wide range of high-performance MIPS32 processor cores which will form the basis for the company's continued penetration of the high ... read more

IC Manage to Deliver Next Generation IC Design Data Management System 

May 24, 2004 -- IC Manage, Inc. today announced its official company launch, offering its next generation IC design management system to improve designer productivity and eliminate the problems associated with tracking and configuring designs. A ... read more

Magma Announces 90-nanometer Design Enablement Kit for IBM, Chartered Process Platform 

May 24, 2004 -- Magma Design Automation, Inc. has announced the availability of a preliminary 90nm RTL-to-GDSII design enablement kit in support of the recently announced IBM-Chartered cross-foundry design enablement program. Included in the kit ... read more

Virage Logic Teams with Tensilica to Offer Embedded Memory Generator Integrated with Tensilica's Xtensa Processor 

May 24, 2004 -- System-on-chip designers can now quickly evaluate and select the optimal embedded memory intellectual property (IP) for their Tensilica Xtensa processor configurations using a new web-based portal interface. Created by Virage Log ... read more

IBM, Chartered Expand 90nm Joint Design Enablement Program, Enhance Foundry Compatibility with Key EDA Support 

May 24, 2004 -- IBM and Chartered Semiconductor Manufacturing have announced support from leading EDA suppliers for their cross-foundry design enablement program, starting at 90nm.

Under separate collaborations also announced today, the ... read more




 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.550  2.1875