| QuickLogic Announces Integration of Magma’s Palace into Quickworks Development Tools |
May 11, 2004 – QuickLogic Corp. today announced that Palace, Magma Design Automation's physical synthesis tool for programmable logic devices, now supports its mWatt Eclipse II and Eclipse FPGA products as well as its QuickMIPS family of ESP pro ... read more |
| Altera Offers FPGA-Based Hardware Reference Platforms for DDR2, RLDRAM II, and QDRII Memories |
May 11, 2004 -- Altera Corp. has introduced two FPGA-based hardware reference platforms for use with DDR2 SDRAMs, QDRII SRAMs and RLDRAM II memory devices. Using Stratix FPGAs to implement high-speed memory interfaces, these reference platforms ... read more |
| Synopsys and Philips Announce New Philips' CoolFlux DSP Core to be Distributed in Synopsys' DesignWare Library |
May 11, 2004 -- Synopsys, Inc. and Philips are collaborating to give designers access to Philips' ultra-low power CoolFlux DSP core through Synopsys' DesignWare Star IP program. The CoolFlux DSP is the first DSP core in the DesignWare Star IP p ... read more |
| Digital Core Design Releases New Media Access Controller Core |
May 11, 2004 -- Digital Core Design's DMAC 10/100 Mb Media Access Controller is a hardware implementation of media access control protocol defined by the IEEE standard. It is developed as an extension peripheral to use with DCD's and customer's ... read more |
| Legend Announces Software Tool for Process Optimization, Verification and Statistical Characterization |
May 10, 2004 -- Legend Design Technology, Inc. has announced that the CharFlo-Memory! software has been extended to CharFlo-Memory!-TD for semiconductor process optimization, verification, and statistical characterization. The purpose is to enh ... read more |
| Forte Announces Cynthesizer Behavioral Synthesis using SystemC |
May 10, 2004 -- Forte Design Systems has introduced Cynthesizer, the first behavioral synthesis product to offer an implementation path from SystemC to RTL, verification, and co-simulation. Cynthesizer accelerates RTL delivery for integrated c ... read more |
| Forte Design Systems Announces Opening of Forte KK in Japan |
May 10th, 2004 -- Forte Design Systems, Inc. has announced the official opening of Forte Design Systems KK. The wholly owned subsidiary will provide sales and support services for Japanese customers. Ikuo Yamada will lead the Shin Yokohama-based ... read more |
| Xilinx Introduces QPRO Virtex-II Family |
May 10, 2004 -- Xilinx, Inc. has announced the immediate availability of its QPRO Virtex-II radiation-tolerant reconfigurable Platform FPGA family. The family offers densities of up to six million system gates and system features such as high p ... read more |
| Denali Launches PureSuite Verification Suite for Compliance, Interoperability of PCI Express Designs |
May 10, 2004 -- Denali Software, Inc. has introduced PureSuite, a comprehensive verification suite that exercises PCI Express designs and measures both compliance with the PCI Express specification and interoperability with other PCI Express des ... read more |
| Altera Stratix Devices Enable Broadband Physics' SDM Technology |
May 10, 2004 -- Altera Corp. and Broadband Physics have announced that Altera's programmable logic solutions enabled the implementation of Broadband Physics' Sub-band Division Multiplexing (SDM) technology to increase digital capacity from cable ... read more |
| Atrenta Teams Up With VSI Alliance to Develop an Automated Method to Validate IP Quality |
May 10, 2004 -- Atrenta, Inc. has joined the Virtual Socket Interface Alliance (VSIA), the SoC, IP, and reuse standards group driving system chip productivity. Atrenta is partnering with VSIA's Quality IP (QIP) development working group to imple ... read more |
| BAE Systems and Celoxica Unveil Biometrics and Real-Time Video Technology Demonstrators |
May 10, 2004 -- BAE Systems and Celoxica, Ltd. have announced plans for the first public demonstration of safety and security applications, in the Celoxica booth at the 41st Design Automation Conference in San Diego from June 7-11.
The de ... read more |
| CEVA Announces Foundry Program Partnership with Tower Semiconductor |
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May 10, 2004 -- CEVA, Inc. has announced that Tower Semiconductor, Ltd. has joined CEVA's foundry program and will offer CEVA's Xpert-Teak DSP platform to its customers. Xpert-Teak is a complete DSP system-on-chip framework built around CE ... read more |
| CoWare Joins UWB Forum and Announces Addition of DS-UWB Library to SPW |
May 10, 2004 -- CoWare, Inc. has announced the addition of direct sequence ultra wideband (DS-UWB) technology to its SPW wireless LAN library. In addition, CoWare announced it has joined the UWB Forum, the industry organization backing DS-UWB t ... read more |
| IntruGuard Devices Partners with QualCore Logic for Implementation of Network Denial of Service ASICs |
May 10, 2004 -- IntruGuard Devices haspartnered with QualCore Logic's Design Realization Team to implement IntruGuard's patent-pending design for the recently announced IG2000 rate-based Denial of Service (DoS) appliance.
The IG2000 protec ... read more |
| Xilinx Completes Successful UNH Interoperability Testing for Ethernet Solutions Suite with Virtex-II Series FPGAs |
May 10, 2004 -- Xilinx, Inc. has announced that its Ethernet solutions suite has successfully completed interoperability testing at the University of New Hampshire's Interoperability Lab (UNH IOL). Xilinx is working with the UNH IOL to ensure t ... read more |
| Synopsys' SiVL Silicon-Versus-Layout Verification Tool Enhancements Enable Faster Time-to-Yield |
May 10, 2004 -- Synopsys, Inc. has announced substantial enhancements to SiVL, a silicon-versus-layout (SVL) verification tool and key component of Synopsys' design-for-manufacturing (DFM) solution. SiVL compares a target design to its simulate ... read more |
| Nassda Releases Version 5.0 of HANEX with Spice-Accurate Hierarchical Timing Analysis |
May 10, 2004 -- Nassda Corp. has released HANEX version 5.0 for circuit-level timing and crosstalk analysis of custom digital designs at 130nm processes and below. Highlights of this new release include hierarchical timing analysis, enhanced pos ... read more |
| Rambus Provides DDR and GDDR Memory Controller Interface Cells and Services |
May 10, 2004 -- Rambus, Inc. has announced the availability of a family of double data rate (DDR) memory controller interface cells and services. Providing support for mainstream DDR1 and DDR2 up to 800MHz data rates and graphics DDR, including ... read more |
| TI Extends imec Relationship with Core Membership; Research Teams Expand Exploration of Advanced Processes |
May 7, 2004 -- Expanding a 12-year relationship with IMEC, Texas Instruments, Inc. has announced it is becoming a core member of the sub-45nm CMOS research program. The move to core membership grows the total number of programs TI will participa ... read more |
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