May 15, 2006 -- Aldec, Inc. announced today that Lattice Semiconductor Corp. has validated Aldec's Riviera and Active-HDL simulators for use with Lattice devices. Mutual customers can now utilize Aldec's simulators in conjunction with Lattice's ispLEVER 6.0 design environment when implementing Lattice devices. The ispLEVER 6.0 programmable logic design tool suite is a complete design environment for all Lattice digital FPGA devices. The addition of Aldec's simulation technology support in ispLEVER 6.0 allows mutual customers to utilize Aldec's HDL simulation technology as well as co-simulation support for Matlab and Simulink.
"Aldec continues to see wide-spread customer interest in the latest Lattice device offerings," stated David Rinehart, Vice President of Marketing at Aldec. "Lattice's use of our simulator in the validation process of their libraries, including the newest 90-nm devices, enables Aldec to fully support designers using the latest Lattice devices."
"The Lattice ispLEVER 6.0 design tool suite includes support for the industry's fastest 90-nm FPGAs," said Tim Schnettler, Director of Design Tools Marketing at Lattice. "By validating our libraries at the factory using Aldec's simulation technology we are able to provide our mutual customers with a synchronized release and the highest quality support."
Go to the Aldec, Inc. website to find additional information.