October 31, 2006 -- The MathWorks, Inc. today introduced Link for Cadence Incisive, which offers verification of hardware description language (HDL) implementations based on MATLAB and Simulink models. Link for Cadence Incisive integrates MATLAB and Simulink with the Incisive functional verification platform from Cadence Design Systems, Inc., for efficient design and verification of SoC, ASICs, and FPGAs through cosimulation. By providing a bidirectional path between MathWorks system models and Incisive simulators, Link for Cadence Incisive simplifies and accelerates the verification process, reducing the design time and errors associated with traditional verification methods.

"Link for Cadence Incisive combines the power of Model-Based Design using MATLAB and Simulink with the comprehensive hardware simulation capabilities of the Incisive platform," said Colin Warwick, Technical Marketing Manager at The MathWorks. "The MathWorks collaboration with Cadence has helped solve a large verification bottleneck in integrated circuit design. It has eliminated the need for time-consuming and unreliable methods like handwritten HDL or Perl scripts."

Engineers can reuse test benches developed in Simulink with verification environments created using the Incisive platform for full system-level verification. This flexibility lets them verify, before tape out, that their HDL implementation matches the executable specification previously validated in MATLAB and Simulink.

Link for Cadence Incisive supports three workflows – Simulink cosimulation, MATLAB test bench, and MATLAB component – that offer full interactive debug capability in both client and server. Link for Cadence Incisive can interface to multiple HDL entities and Incisive simulators from a single MATLAB test bench or Simulink model.

Pricing and Availability