Page loading . . .

  
 Category: News: News Archive 2006: Sunday, May 19, 2013
Sort Entries by    
Use the input form on the right to search on a word or phrase.  
Page(s): 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 (2505 Entries)
Aprio and Silicon Canvas Present DFM-Aware Layout Product 

July 12, 2006 -- As part of a series of announcements, Aprio Technologies, Inc. and Silicon Canvas, Inc. today disclosed collaboration to provide a design for manufacturability (DFM) aware layout product. By integrating Aprio's Hal ... read more

OCP-IP Releases PSL Package 

July 12, 2006 -- OCP International Partnership (OCP-IP) has announced the availability of an OCP Property Specific Language (PSL) package to aide in verification of IP blocks. The PSL package compliments traditional verification methodolo ... read more

Cswitch to Preview Configurable Switch Array Chip Technology at DAC 2006 

July 12, 2006 -- Cswitch Corp. will preview its Configurable Switch Array chip technology at the 43rd Design Automation Conference (DAC) held from July 24-28 in San Francisco. The new architecture offers performance levels approaching an ... read more

Cswitch and Denali Team on PCI Express for Configurable Switch Array Chip 

July 12, 2006 -- Denali Software, Inc. and Cswitch Corp. today announced results of a collaborative effort to deploy Denali's Databahn PCI Express core on Cswitch's Configurable Switch Array chip. They successfully integrated the Databahn ... read more

Javelin Design Automation Emerges from Stealth to Introduce System Physical Prototyping 

July 12, 2006 -- Startup Javelin Design Automation has emerged from stealth to announce first-of-its-kind technology – System Physical Prototyping (SPP) – to enable evaluation of early architecture tradeoffs and logic feasibility based o ... read more

Incentia Announces TimeBench Timing Environment for Nanometer Designs 

July 12, 2006 -- Incentia Design Systems, Inc. today introduced TimeBench, a complete timing analysis, management and debugging environment for 90- and 65-nm designs. TimeBench is built on Incentia's static timing tool and addresses the m ... read more

Aprio's Halo-Quest Yields Highly Accurate Silicon Image Data 

July 12, 2006 -- As part of its unified design-for-manufacturability (DFM) strategy, Aprio Technologies, Inc. has announced Halo-Quest, a new application that generates a highly accurate silicon image representation of an integrated circu ... read more

Aprio Previews Hardware-Assisted Mask Layout Repair Solution 

July 12, 2006 -- Aprio Technologies, Inc. will provide an initial demonstration of the results of its development collaboration with KLA-Tencor Corp. at this year's Design Automation Conference, to be held at San Francisco's Moscon ... read more

Synopsys 2006.06 Release of DesignWare Library Reduces Area and Delay in IC Designs 

July 12, 2006 -- Synopsys, Inc. has expanded its DesignWare Library intellectual property (IP) by adding more than 20 new components. The additions include 10 floating point operations and four complex datapath functions. When used with S ... read more

Ponte and Pyxis Form Alliance to Streamline Yield Sensitivity Analysis and Optimization for Sub-100-nm Designs 

July 12, 2006 -- Pyxis Technology, Inc. and Ponte Solutions, Inc. have formed an alliance to bridge the gap between design and manufacturing by bringing together the design for manufacturability (DFM) routing technology from Pyxis and yie ... read more

Genesys Testware Adds Top-Down Insertion of Test and Repair Circuits for Embedded Memory  

July 12, 2006 -- Genesys Testware, Inc. announced today the addition of top-down insertion of test and repair circuits for embedded memory to its ArraytestMaker product. The Genesys top-down solution enables system IC designers to inser ... read more

Cypress's SVTC Enables Cavendish Kinetics to Develop and Characterize Embedded Non-Volatile Memory Technology for Standard CMOS Processes 

July 12, 2006 -- Silicon Valley Technology Center (SVTC), a business unit of Cypress Semiconductor Corp. today announced that Cavendish Kinetics, Inc. is using SVTC's technology development services to commercialize its Nanomech e ... read more

austriamicrosystems AS1150-52 Quad LVDS Family Significantly Reduces Power Consumption for High Speed Data Transmission 

July 12, 2006 -- austriamicrosystems AG has unveiled the first products in its new family of low-voltage differential signaling (LVDS) ICs that are suited to applications requiring high-speed data transmission, such as digital copiers, la ... read more

JTAG Technologies Supports Altera Stratix II FPGA Design Security 

July 12, 2006 -- JTAG Technologies, Inc. today announced that its boundary-scan tools now support the advanced security features of Altera Corp.'s Stratix II FPGA family. Users of JTAG Technologies tools are able to perform in-syst ... read more

Microchip Technology Expands 20-Pin PIC Microcontroller Family 

July 12, 2006 -- Microchip Technology, Inc. has announced two new 20-pin PIC microcontrollers to further strengthen its 8-bit portfolio. The PIC16F631 provides a cost-effective entry point for migration from 8- and 14-pin devices, while t ... read more

Empower Technologies and TI Streamline Consumer Electronic Development 

July 12, 2006 -- Empower Technologies and Texas Instruments, Inc. (TI) today announced the release of Empower's latest LinuxDA Embedded Operating System (LEOs 2.3) running Linux Kernel 2.6.12 along with TI's DSP/BIOS Link for TI's OMAP591 ... read more

Ateme Launches EASEE Audio/Video Software System for TI's DaVinci Technology 

July 12, 2006 -- Enabling developers to benefit from Texas Instruments, Inc.’s (TI) DaVinci technology, Ateme has developed an Audio/Video Software System called EASEE. The Software System running on Linux resolves all lip synch is ... read more

Sequans Announces Availability of Mobile WiMAX Chip 

July 12, 2006 -- Sequans Communications is now sampling its WiMAX mobile station chips to select customers. Supporting the recently ratified 802.16e-2005 broadband wireless access standard, the chip provides equipment makers with a fully ... read more

Micron Becomes 9th Core Partner within imec's sub-32nm Research Platform 

July 12, 2006 -- imec today announces that Micron Technology, Inc. has joined IMEC's sub-32-nm CMOS research platform as a core partner. Micron will also participate within IMEC's advanced Flash memory program. With Micron joining ... read more

Solarflare Selects XJTAG Boundary Scan to Debug and Test Ethernet Network Cards 

July 12, 2006 -- Solarflare Communications, Inc. a fabless semiconductor company that provides high-performance Ethernet solutions, has selected the XJTAG's boundary scan solution to debug and test its EtherFabric EF1-21022T Networ ... read more




 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.552  4.578125