| Berkeley Design Automation Launches Analog FastSpice and RF FastSpice |
July 24, 2006 -- Berkeley Design Automation, Inc. has launched two products that establish a new category of advanced circuit verification tools. Analog FastSpice and RF FastSpice deliver full-Spice accuracy at 5X to 10X performance with ... read more |
| Carbon Adds Replay to its SOC-VSP Offering |
June 22, 2006 -- Carbon Design Systems, Inc. announced today that it will introduce major new functionality for its SOC-VSP product line at this year's Design Automation Conference. ESL simulation environments typically contain models at ... read more |
| Open SystemC Initiative Ensures Global Access of IEEE Std. 1666-2005 LRM at No Cost to Users Featured |
July 18, 2006 -- The Open SystemC Initiative (OSCI) has announced the public availability of the IEEE 1666(TM)-2005 Standard SystemC Language Reference Manual (LRM) now accessible on the IEEE website. In addition, a companion o ... read more |
| Jasper Design Automation Announces JasperGold Verification System 4.2 |
July 19, 2006 -- Jasper Design Automation today announced JasperGold Verification System 4.2, a new release of the company's flagship formal verification solution that dramatically improves both novice and advanced user experience, and al ... read more |
| Jasper Unveils Free Tool for Easy Generation of Structured Verification Plans |
July 19, 2006 -- Addressing one of the key problems facing verification teams today, Jasper Design Automation unveiled GamePlan Verification Planner, a new tool being offered at no cost that generates and tracks the progress of verificati ... read more |
| SoftJin Announces Building Block for Logic Optimization and Mapping |
July 18, 2006 -- SoftJin Infotech Pvt. Ltd. today announced its new Programmable Synthesis Engine (PSE), a logic optimization and mapping software product that is customizable for a variety of programmable platform architectures, such as ... read more |
| Jasper Design Automation Integrates Verific's SystemVerilog Component Software with JasperGold Verification System |
July 20, 2006 -- Verific Design Automation, Inc. today announced that Jasper Design Automation has integrated Verific's SystemVerilog Component Software with JasperGold Verification System. In addition to SystemVerilog component so ... read more |
| Silistix and CoWare Developing ESL-Based Design Flow for Chips Using Asynchronous Self-Timed Interconnect |
July 20, 2006 -- Silistix, Ltd. is developing solutions for SystemC electronic system level (ESL) SOC development using Silistix's CHAIN self-timed interconnect fabric. The company will integrate Silistix's CHAINworks tool suite with C ... read more |
| Verific Adds Liga Systems to List of Users |
July 19, 2006 -- Liga Systems, Inc. announced today that Verific Design Automation, Inc.'s hardware description level (HDL) Component Software will serve as the register transfer level (RTL) front end for NitroSIM, its Hybrid Simul ... read more |
| Silicon & Software Systems (S3) Announces 90-nm CMOS IP Licensing Agreement for Mobile TV Applications |
July 21, 2006 -- Silicon & Software Systems, Ltd (S3) today announced that Abilis Systems has licensed S3's low power ADC IP in 90-nm CMOS process. Abilis will incorporate S3’s analog-to-digital converter (ADC) IP into its first g ... read more |
| AWR and Peregrine Semiconductor Collaborate to Develop Design Kit for Peregrine's UltraCMOS Process |
July 20, 2006 -- AWR Corp. and Peregrine Semiconductor Corp. have announced the availability of a process design kit (PDK) for Peregrine's UltraCMOS silicon-on-sapphire (SOS) process in AWR's Analog Office design suite, a software ... read more |
| Summit Design Vista IDE Enhances Its SystemC Debugging Capabilities with IEEE 1666 and Windows Platform Support |
July 18, 2006 -- Summit Design, Inc. has announced important enhancements to its Vista integrated design environment (IDE) for SystemC. Vista 2006.1 adds support for IEEE 1666, the standard for SystemC from the Open SystemC Initiative ( ... read more |
| Sonics and Summit Design Team to Accelerate Industrywide SystemC Platform SoC Transformation |
July 19, 2006 -- Sonics, Inc. and Summit Design, Inc. have announce a broad agreement by which Summit will distribute SystemC language versions of Sonics' SMART Interconnect solutions that operate seamlessly within Summit's Panoram ... read more |
| Axiom Accelerates All Aspects of Functional Verification Including Testbench Parallelization |
July 20, 2006 -- Axiom Design Automation today announced that it has achieved a major improvement in functional verification performance by enabling SystemVerilog and OpenVera testbench parallelization. The testbench has long been the pri ... read more |
| Apache Announces Sahara-PTE Integrated Power-Thermal-Electrical Solution for SOC Designs |
July 21, 2006 -- Apache Design Solutions, Inc. has announced Sahara-PTE, a fully integrated electro-thermal solution for SOC temperature's impact on leakage, timing, reliability, and voltage drop. Sahara's tightly integrated power-thermal ... read more |
| Gradient Design Automation Brings IC Thermal Verification to UMC |
July 21, 2006 -- Gradient Design Automation, Inc. today announced that UMC (United Microelectronics Corp.) has agreed to implement Gradient's products into an IC thermal verification flow, with the goal of ensuring that customer d ... read more |
| Accellera Approves VHDL Applications Programming Interface Standard to Improve Design Portability Featured |
July 21, 2006 -- Accellera announced today that its members approved a new VHDL standard, a VHDL Applications Programming Interface (API) known as VHPI, late last month. This standard was transferred to the IEEE for its consideration as ... read more |
| Synopsys Delivers First 65-nm Reference Flow for IBM, Samsung and Chartered |
July 21, 2006 -- Synopsys, Inc. has announced availability of its extended RTL-to-GDSII low-power reference design flow for the latest 65-nm process offered by the IBM-Chartered Semiconductor Manufacturing-Samsung Common Platform technolo ... read more |
| FSA Introduces Mixed-Signal/RF PDK Checklist Version 2.0 Featured |
July 21, 2006 -- Fabless Semiconductor Association (FSA) today announced the release of its Mixed-Signal/RF Process Design Kit (PDK) Checklist version 2.0. The Checklist documents the contents of a PDK, a set of data files that enable ana ... read more |
| Magma Announces Integrated Characterization-to-Silicon DFM Flow Targeting 65-nm Designs |
July 17, 2006 -- Magma Design Automation, Inc. has announced a comprehensive new design-for-manufacturability (DFM) methodology targeting sub-nanometer designs. The Characterization-to-Silicon DFM flow includes the new SiliconSmart DFM fo ... read more |
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