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TLM-Driven Design and Verification: Time for a Methodology Shift

While today's RTL design and verification flows are a step up from the gate-level flows of two decades ago, RTL flows are straining to meet the demands of most product teams. When designs are sourced and verified at the register-transfer level (RTL), IP reuse is difficult, functional verification is lengthy and cumbersome, and architectural decisions cannot be confirmed prior to RTL verification. With increasing pressure on today's SOC and ASIC design teams to deliver more aggressive designs in less time, and the need to get designs right on the first pass, many companies are looking to move to the next level of abstraction beyond RTL to get a much-needed boost in design productivity.

Read the entire article from Cadence Design Systems, Inc. on SOCcentral.

SCE-MI Explained: Macro-based and Function-based

SCE-MI stands for Standard Co-Emulation Modeling Interface and is the Accellera standard for bridging two realms: un-timed (HLV, on a host) and timed (HDL, in an emulator). The main goal was to eliminate communication bottlenecks that could compromise performance of hardware emulation systems, such as Aldec's HES, that could run in the 10-MHz range. This is why communication channels are transaction-oriented, not event-oriented as in simulation acceleration. The idea is that a single message from software could trigger hundreds of clock cycles in hardware, and similarly, hundreds of hardware clock cycles are needed to form a message for software. This is achieved using synthesizable transactors — bus functional models that reside in hardware and translate function calls into sequences of bits — reducing the bandwidth required for software/ hardware communication and allowing an emulator to run closer to its full speed.

Read the entire article from Aldec, Inc. on SOCcentral.

Extending the Metric-Driven Verification Methodology to TLM

Metric-driven verification (MDV) has established itself as a powerful approach to verification, beginning with RTL. By planning the verification process with clearly defined metrics and tracking progress toward those goals, the MDV approach reaches verification closure more efficiently and with a higher level of confidence. We see increasing demands in the industry for this extended MDV approach, and we describe one such solution addressing hardware IP verification. The primary users of this solution are the verification teams for hardware IP design divisions, who provide a sign-off procedure for the IP. This article first observes the types of models of such IP that are often written at abstraction levels higher than RTL and are useful for verification. It then presents how the existing verification methodology at RTL can be naturally extended to start the verification work early using those models.

Read the entire article from Cadence Design Systems, Inc., Inc. on SOCcentral.

Hardware in the Software Sphere of Influence

The increasing prevalence of multi-core design and concurrent software execution makes it ever more critical to be able to validate hardware and software processes in concert under system-level scenarios. This level of verification cannot be conducted at the RTL design stage for several reasons. Simulation is too slow to execute any meaningful software and simulate realistic scenarios; RTL redesign is too costly; and finding system-level bugs at the RTL abstraction is too complicated. Industry-compliant SystemC TLM2.0 (transaction level models) can simulate on any industry-compliant SystemC simulator without requiring proprietary extensions. In addition, TLM2.0 contains specific enhancements that enable very efficient communication for optimal simulation speed.

Read the entire article from Mentor Graphics Corp. on SOCcentral.

Realizing ESL with Scalable Transaction-Level Models

The effectiveness and productivity of RTL modeling and verification techniques are sinking under the weight of growing design complexity. Traditional design and verification methodologies were not intended to address the billions of transistors, intricate hardware/ software interfaces, and complex device architectures of today’s consumer, mobile, networking, and storage systems. As a result, design flows will inevitably shift toward the electronic system level (ESL).

Read the entire article from Mentor Graphics Corp. on SOCcentral.