Featured Articles
 |
Reaching for the Cloud: What's Next for Interconnects
As the nerve center of the SOC, it is critical that the on-chip network keep pace with all the high-performance subsystems and does not become the system bottleneck. The increased bandwidth capabilities of multi-channel DRAM systems, coupled with the emergence of system-level coherence across subsystems, is driving on-chip network frequencies above 1GHz. As a result, the on-chip network will continue to take on an even more critical role in SOC design as integration, headroom and complexity requirements increase — in the cloud and beyond. ... read more.
By Drew Wingard, Chief Tecnical Officer, Sonics, Inc.
|
|
A Layered Approach to NoC
The challenge of on-chip communication traffic is presently compounded in two ways: First, use of multiple processors and cores with single or multiple memories in system-on-chips (SOCs) are driving the need for a lower cost, easier to design and more elegant on chip communication solution. Second, existing bus-based interconnect architectures and techniques are proving to be non-scalable, unable to meet leading edge complexity and performance requirements. Both issues create unprecedented challenges in achieving timing closure and meeting the power requirements of today’s most sophisticated consumer, communications and computing applications.
Fortunately, new approaches have emerged, most notably Network on Chip (NoC), to allow efficient and high-performance on-chip communications for complex SOC designs. The NoC has a key advantage in that it uses fewer global wires than a bus and those wires that it uses are point-to-point. This allows a NoC to operate with half the power of a bus at the same operating frequency while offering over three times the operating frequency. System bandwidth is easily adjusted by increasing the width of NoC links and switches. Scalability of a NoC supports SOCs comprising hundreds of IPs with concurrent support for multiple IP protocols. However, even within the emerging NoC space, there are differing approaches that meet these basic requirements.
Read the entire article from Arteris SA on SOCcentral.
On-Chip Interconnects for Multi-Core Chips: A Software Perspective
Portable and distributed multi-media applications are driving an ever increasing demand for computational performance at acceptable power consumption levels, both at the client and the infrastructure sides. At the same time, the software content driven by functional requirements is constantly increasing and is already in the millions of lines of code in some devices. Parallel processing offers power consumption relief but it brings new challenges as well. A number of multi-core chips are already in the market and with shrinking silicon geometries we will see an increasing number of (homogenous and heterogeneous) cores per chip.
Most of the current dual-core chips have shared memory and a bus. While the bus and shared memory architecture is quite simple from a programming perspective (the cores can easily exchange data), the bus will become a bottleneck as the number of cores increase. We can, therefore, expect to see more and more types of interconnects, such as multi-level buses, crossbars, point-to-point, mesh, network-on-chip, etc., in different logical structures, as well as non-uniform memory architectures much like they have been used at the board level and beyond for a long time. Effective interconnect systems are, or will become, as important for multi-core chips as efficient caches for a single processor.
Read the entire article from PolyCore Software, Inc. on SOCcentral.
|
Magazine & Journal articles about On-Chip Interconnect |
| Customizing SRAM Content to Obtain Truly Differentiated Products Chip Estimate Corp. (5/14/2013) |
| Boost DFT Efficiency for Large SOCs Test & Measurement World (4/23/2013) |
| SOC FPGAs Combine Performance and Flexibility EDN Magazine (4/10/2013) |
| SSM Policy-Driven System Management Updates SOC Architecture to Meet Today's Operation Complexities Chip Estimate Corp. (4/9/2013) |
| Building Your UVM Verification Environment for Cache-Coherent Interconnects Design & Reuse (4/4/2013) |
| Communication-Centric Test and Debug Infrastructure for Multicore SOCs Design & Reuse (3/28/2013) |
| Smart Decap-Insertion Methodology Design & Reuse (3/18/2013) |
| Hardware (and Software) Implications of Endianness in SOC Design Embedded.com (3/17/2013) |
| Formal Verification Works Well for Connectivity Checking SOCcentral (3/15/2013) |
| Optimizing Clock-Tree Distribution in SOCs with Multiple Clock Sinks Embedded.com (3/10/2013) |
| Analyzing the Options in High-Bandwidth System Interconnect Altera Corp. (3/8/2013) |
| Smart Power Hook-Up Methodology for Memories on SOCs EDN Magazine (1/16/2013) |
| The SOC Interconnect-Verification Challenge SOCcentral (1/14/2013) |
| Texas Instruments Puts ARM-DSP Processors Into Play for HPC HPCwire (11/20/2012) |
| Memory Solution Addressing Power and Security Problems in Embedded Designs EE Times EDA Designline (10/22/2012) |
| Understanding 28-nm SOC Design with ARM-Based Cores Electronic Design Magazine (10/19/2012) |
| What's the Deal with SOC Verification? Electronic Design Magazine (10/10/2012) |
| Use the Power of Your SOC to Verify Its Low-Power Design Features SOCcentral (9/1/2012) |
| Growing Audio Requirements in SOCs EE Times Audio Designline (8/23/2012) |
| Solutions for Mixed-Signal SOC Verification SOCcentral (8/21/2012) |
| Understanding FPGA Processor Interconnects Electronic Design Magazine (7/17/2012) |
| Streamlining Design Using Macro Placement Algorithms in Mixed-Signal SOCs EE Times Embedded (7/16/2012) |
| Power Is on Everybody's Mind SOCcentral (6/29/2012) |
| Sexy SoCs Are Not the Whole Story for FPGAs Electronics Weekly (6/18/2012) |
| Designing Embedded SOCs Using Older Resistive Technologies EE Times Embedded (5/30/2012) |
| Pseudo-Hardening in SOC Design EDN Magazine (5/25/2012) |
| Decoupled Constraint Modelling: A Design Methodology for Hard Real-Time SOCs Tech Design Forum (5/15/2012) |
| Integrating High-Level Synthesis Design into FPGA SOCs with Less Effort and Risk DSP-FPGA (5/15/2012) |
| 3D IC 2-tier 16PE Multiprocessor with 3D NoC Architecture Based on Tezzaron Technology Design & Reuse (5/14/2012) |
| An Accurate DRAM Model SOCcentral (5/14/2012) |
| Augmenting the Transaction Generator with New DRAM and Workload Models SOCcentral (5/11/2012) |
| Interconnect Modeling at 20nm: More of the Same or Completely Different? Electronic Engineering Times (EE Times) (5/10/2012) |
| Verifying Today's SOCs Requires a New Approach Electronic Engineering Journal (5/3/2012) |
| Reaching for the Cloud: What's Next for Interconnects SOCcentral (4/27/2012) |
| SOC Low-Power Verification Requires a Full-Chip Solution Electronic Engineering Times (EE Times) (4/13/2012) |
| Design Industrial Systems on a Chip that Meet Stringent Global Safety Standards EE Times Industrial Control Designline (1/18/2012) |
| Define Drain-Current Conditions when Calculating Power for Multicore SOCs EE Times Automotive Designline (1/5/2012) |
| Reducing Sign-Off Corners to Achieve Faster 40-nm SOC Design Closure EE Times Embedded (12/20/2011) |
| Prototyping Mesh-of-Tree NOC-Based MPSOC on Mesh-of-Tree FPGA Devices Design & Reuse (11/23/2011) |
| A Brief Primer on Embedded SOC Packaging Options EE Times Embedded (11/20/2011) |
| Multi-FPGA NOC Based 64-Core MPSOC: A Hierarchical and Modular Design Methodology Design & Reuse (10/19/2011) |
| Advanced Sign-Off…It's Trending! SOCcentral (9/13/2011) |
| SOC Ecosystems Become More Tightly Integrated Chip Design Magazine (8/1/2011) |
| Creating an SOC Virtual Platform for Embedded Software Development Electronic Design Magazine (6/28/2011) |
| Application Driven Network on Chip Architecture Exploration & Refinement for a Complex SOC Design & Reuse (6/20/2011) |
| Basics of SOC I/O design-Part 2: Hot Swap & Other Implementation Issues EE Times Embedded (6/14/2011) |
| Basics of SOC I/O Design-Part 1: The Building Blocks EE Times Embedded (6/13/2011) |
| STAC: Advanced Inter-Die Communication Technology Design & Reuse (5/18/2011) |
| IP Gets Smarter SOCcentral (4/1/2011) |
| Automating Design Rule Waivers in SOC IP Reuse Design & Reuse (3/31/2011) |
| Using Simulation and Emulation Together to Create Complex SOCs EE Times EDA Designline (3/23/2011) |
| Analog IP for Multimedia SOCs: An Eye on a World of Essential Analog Features EE Times Planet Analog (3/22/2011) |
| What Makes an Optimal SOC Verification Strategy EE Times EDA Designline (3/21/2011) |
| System Awareness Improves SOC Power Management EE Times Power Management Designline (3/18/2011) |
| Hardware/Software Integration: Closing the Gap EE Times EDA Designline (3/13/2011) |
| Virtual Channels Hardware Support in Switches in Relation to NoC Costs, Functions and Features Design & Reuse (2/21/2011) |
| Using SystemC to Build a System-on-Chip Platform EE Times Embedded (2/2/2011) |
| Quest Continues for the "Sweet Spot" in Configurable ASIC/ SOC Design RTC Magazine (1/1/2011) |
| Critical False-Path Analysis Through Sensitization Methods EDN Magazine (12/29/2010) |
| Choosing an Effective Embedded SOC ASIC Design Strategy EE Times Embedded (12/13/2010) |
| Deadly Reasons for Extraction Failure SOCcentral (12/13/2010) |
| A Memory Subsystem Model for Evaluating Network-on-Chip Performance Design & Reuse (12/2/2010) |
| SOC-PLL Design Requires Trade-Offs EDN Magazine (12/2/2010) |
| SOC DFT Verification With Static Analysis and Formal Methods Test & Measurement World (11/17/2010) |
| eFPGA Creator GUI Tools Suite: A Complete Hardware and Software Infrastructure for Creating Customizable eFPGA IP Blocks Design & Reuse (11/4/2010) |
| Will IP Use Increase In Forthcoming SOC Design? Electronic Engineering Times (EE Times) (11/4/2010) |
| Hyper Pipelining of Multicores and SOC Interconnects EE Times EDA Designline (11/2/2010) |
| A Next-Gen FPGA-Based SOC Verification Platform EE Times Programmable Logic Designline (11/1/2010) |
| HW/SW Interface Generation Flow Based on Abstract Models of System Applications and Hardware Architectures Design & Reuse (10/25/2010) |
| Design Environment for the Support of Configurable Network Interfaces in NoC-based Platforms Design & Reuse (10/21/2010) |
| Conquering the Memory Bottleneck EE Times Memory Designline (9/13/2010) |
| Dual-Core Architectures In Automotive SoCs EE Times Automotive Designline (8/23/2010) |
| IP Integration: Is It the Real System-Level Design? EDN Magazine (8/16/2010) |
| Use XML to Build ASIC or SOC Design Specifications EE Times Embedded (7/31/2010) |
| Power-Grid Analysis on SOC Graphics Chip Design EDN Magazine (6/17/2010) |
| Continuous Integration of Complex Reconfigurable Systems Design & Reuse (5/20/2010) |
| Building Cost-Effective and Robust SOC-based Network Appliances EE Times Embedded (5/17/2010) |
| A Novel Mesh Architecture for On-Chip Networks Design & Reuse (5/16/2010) |
| An Analysis of Blocking versus Non-Blocking Flow Control In On-Chip Networks Design & Reuse (4/22/2010) |
| Integrating Analog Video Interface IP Into SOCs Delivers Superb Image Quality: Part 1 EE Times EDA Designline (4/7/2010) |
| RTL Synthesis Can Accelerate the Entire Implementation Flow EE Times EDA Designline (3/31/2010) |
| Building Quality Assurance Into Your Hardware: EDA Is Not Enough! EE Times EDA Designline (3/17/2010) |
| Selecting an Embedded MCU: How to Avoid the Evaluation Trap? Design & Reuse (3/11/2010) |
| Evolving to a Total IP Solutions to Accelerate SOC Design Design & Reuse (3/4/2010) |
| Incorporating Quality Into Reusable IP EE Times Embedded (2/26/2010) |
| Combating Congestion In High-performance, Low-cost SOCs EDN Magazine (2/23/2010) |
| Guidelines for Complex SOC Verification EE Times EDA Designline (2/15/2010) |
| Acceleration of Program Execution EDN Magazine (2/3/2010) |
| Integration In the Other Direction EDN Magazine (1/21/2010) |
| A Real Solution for Mixed Signal SOC Verification EE Times EDA Designline (1/7/2010) |
| Designing Serial ATA IP Into Your Embedded Storage Device Design EE Times Embedded (12/14/2009) |
| Easier Cross-Domain Signal Protection for Mixed-Signal SoCs EE Times EDA Designline (12/4/2009) |
| What If the IP You Are Looking for Does Not Exist? Design & Reuse (10/29/2009) |
| A Set of VHDL IPs to Evaluate Performance of Netwoks-on-Chip Design & Reuse (10/22/2009) |
| FPGA-Based Rapid Prototyping of ASIC, ASSP, and SoC Designs EE Times Programmable Logic Designline (10/21/2009) |
| Use of an IP core Development Process to Achieve Time-to-Market and Quality Assurance in a Multi-Project Environment Design & Reuse (10/15/2009) |
| Outsourcing SoC Network Design Just Makes Sense Electronic Design Magazine (10/11/2009) |
| The Key to Seamless and Rapid IP Integration SOCcentral (9/1/2009) |
| Placement of Different Type Nodes In a Network-on-Chip Graph Design & Reuse (8/13/2009) |
| Serial Boot: An Alternative Way of Booting SOC Externally EE Times EDA Designline (8/11/2009) |
| DRAM Technology for SOC Designers and — Maybe — Their Customers EDN Magazine (8/6/2009) |
| Changing SoC Design Methodologies to Automate IP Integration and Reuse EE Times EDA Designline (7/27/2009) |
| Securing SoC Platform Oriented Architectures with a Hardware Root of Trust EE Times Embedded (7/6/2009) |
| Tailored SoC Building Using Reconfigurable IP Blocks Design & Reuse (6/8/2009) |
| Adopting an SOC-based Approach to Designing Handheld Medical Devices EE Times Embedded (5/27/2009) |
| Analog IP Integration in SoCs: Challenges and Solutions Design & Reuse (3/3/2009) |
| Dynamic Instruction Set Load-In Method for a Java SOC Design & Reuse (2/12/2009) |
| An Application Modeling and Hardware Description for Network-on-Chip Benchmarking EE Times Embedded (1/14/2009) |
| Providing Memory System and Compiler Support for MPSoc designs: Part 3, Compiler Support EE Times Embedded (1/7/2009) |
| Taking the Delay Out of Your Multicore Design'S Intra-Chip Interconnections EE Times Embedded (1/7/2009) |
| Providing Memory System and Compiler Support for MPSoc Designs: Part 2, Customization of Memory Architectures EE Times Embedded (1/6/2009) |
| Providing Memory System and Compiler Support for MPSoc Designs: Part 1, Memory Architectures EE Times Embedded (1/5/2009) |
| Use Algorithmic Synthesis to Solve Your FPGA Prototyping and Design Issues Electronic Design Magazine (12/10/2008) |
| Multicore: the Future of SOCs? EDN Magazine (10/30/2008) |
| Multicore SoCs Change Interconnect Requirements Electronic Engineering Times (EE Times) (10/20/2008) |
| Taking the Broad View Components in Electronics (CIE) (10/1/2008) |
| Build Debug and Trace Systems for Multicore SOCs Electronic Design Magazine (8/14/2008) |
| HDL-Design Challenges and Philosophies for Real-World ASIC Implementations EDN Magazine (7/24/2008) |
| Power Trends Point to a Knowledge of Integration EE Times EDA Designline (7/22/2008) |
| Interactive C-code Cleaning Tool Supports Multiprocessor SoC Design EE Times Embedded (7/6/2008) |
| Software Rules the Day in Multicore SoC Design Electronic Design Magazine (4/24/2008) |
| Integrating High-Speed serial I/O: No Snap for SOC Designers EDN Magazine (4/17/2008) |
| Critical Clock-Domain-Crossing Bugs EDN Magazine (4/2/2008) |
| Software-Defined Radio Platforms EE Times EDA Designline (3/24/2008) |
| As SOCs Grow, Test-and-Measurement Instruments Move On-Chip EDN Magazine (2/21/2008) |
| Comparing IP Integration Approaches for FPGA Implementation EE Times Programmable Logic Designline (2/20/2008) |
| Choosing System-on-Chip Processes: A Tough Decision EDN Magazine (1/24/2008) |
| OCP VIP: A Cost-Effective and Robust Qualification Process for Multimedia and Telecom SOC Designs EE Times Embedded (1/9/2008) |
| Case Study of a Complex Video System-on-Chip Electronic Engineering Times (EE Times) (12/3/2007) |
| Traffic Management: A Growing Nightmare for SOC Designers EDN Magazine (11/8/2007) |
| 4G Wireless: Evolution or Watershed in SOC Architectures? EDN Magazine (10/4/2007) |
| How Low Can You Go? A Look at 45-nm IC Design Challenges EDN Magazine (9/13/2007) |
| Single-chip Radios Pose Perplexities for SOC Architects EDN Magazine (8/2/2007) |
| Signal Integrity Analysis in Wireless SoCs EE Times EDA Designline (5/14/2007) |
| How to Choose an RTOS for Your FPGA and ASIC Designs EE Times Programmable Logic Designline (5/9/2007) |
| SoCs Can Hold Key to System Security EE Times Embedded (4/2/2007) |
| Choosing to Use an SIP Rather than an SOC EDN Magazine (3/15/2007) |
| Battling bugs: Embedded Debugging Tactics EDN Magazine (12/1/2006) |
| Modeling Gaps in State-of-the-Art Mixed-Signal SOC Design EDN Magazine (11/23/2006) |
| A Layered Approach to NoC SOCcentral (10/23/2006) |
| Synchronous Interconnect is Hitting the Wall SOCcentral (10/23/2006) |
| Making the Transition from Board Level Design to System-on-Chip SOCcentral (10/17/2006) |
| Miniaturization Enables Innovation; Past, Present, and Future EDN Magazine (9/28/2006) |
| Designers Cast a Skeptical Eye on Mixed-Signal SOCs EDN Magazine (5/11/2006) |
| OCP "Tags" Support High-Performance SoCs eeDesign (EE Times EDA News) (5/8/2006) |
| Mixed-Abstraction Virtual System Prototypes Close SOC Design Gaps SOCcentral (4/14/2006) |
| IP Integration Is Standard Fare Electronic Design Magazine (4/13/2006) |
| Preview USB Performance in an SOC Design Using a SystemC Virtual Platform EDN Magazine (2/16/2006) |
| Compiling FPGA Netlists for Formal Verification eeDesign (EE Times EDA News) (2/6/2006) |
| I/O Planning Ensures IC Packaging Success eeDesign (EE Times EDA News) (1/30/2006) |
| Chip Assembly Challenges and Solutions eeDesign (EE Times EDA News) (1/23/2006) |
| Rail-Signoff Analysis Ensures SoC Power Integrity Electronic Design Magazine (1/19/2006) |
| Designing ASICs for Supersystems Electronic Engineering Times (EE Times) (10/10/2005) |
| Networks on Chip: Challenges and Solutions SOCcentral (7/20/2005) |
|
