Featured Articles
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The IP Distribution Challenge
What comes to mind when you hear the term IP Distribution? How do people like ARM and MIPS get their cores into people's hands? Pricing, contracts and legal issues? Maybe third-party websites like Chip Estimate and Design & Reuse? Yes, they are all factors in how independently developed IP gets distributed to users. But as the commercial IP industry matures, these things are getting much more efficient and well-oiled. ... read more.
By Simon Butler, CEO, MethodICs
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Leapfrogging the Competition Through Smart IP Selection
The adoption of a reliable design reuse methodology, proliferation of high-quality IP products, and shake-out of the most un-trustworthy IP vendors creates a situation offering a huge potential advantage to system integrators and product designers. Instead of choosing the same big-vendor, star IP, smarter firms will seek out and commit to what might be technically superior IP products from smaller vendors/ partners who will offer deeper and broader service and support. ... read more.
By Nikos Zervas, Vice President of Marketing, CAST, Inc.
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DFM-Compliant IP: Why You Need It, How You Get It
To successfully produce designs at 65nm and below, designers must be sure all components of the design have been optimized to reduce the impact of manufacturing process variation. When some of those components are purchased from 3rd parties, designers want to be assured that those components have gone through a rigorous DFM verification process before being incorporated into the design. As we progress from 65nm to 45nm, 32nm, and beyond, and the use of IP components becomes more pervasive, chip designers must continue to have confidence that the IP they bring into their designs has met the highest DFM standards for the applicable process. The establishment of golden DFM standards and methodologies is a critical step in making that assurance possible, and allowing the continued development of complex, high-performing chips at leading process nodes.
Read the entire article from Mentor Graphics Corp. on SOCcentral.
A Processor and DSP IP Selection Checklist
SOC designs are major, high-risk projects and most consist of many IP blocks — some developed in house and some purchased. Many of the most complex blocks are processors and DSPs. With their associated software-development tools, simulation models, and EDA flow scripts, these processor IP blocks affect more than just the hardware design; their influence permeates the entire SOC design project. Consequently, processor IP can literally make or break your project. Here is a list of questions to ask yourself, your team, and any processor IP providers you contact. This list will help you to avoid unhappy IP choices and will help you get exactly what your team needs to develop successful SOC designs on time, within budget, and with minimal hassle.
Read the entire article from Tensilica, Inc. on SOCcentral.
Verification and Automation Improvement Using IP-XACT
Improving the productivity of IP-based design is essential. This tutorial focuses on providing an opportunity to learn more about IP-XACT and how this standard can be used to enhance your IP based design and verification flow.
View the tutorial on the Accellera Systems Initiative website.
The Key to Seamless and Rapid IP Integration
With the ever-growing complexity of IP and accompanying design tools, it's imperative that SOC designers carefully weigh their options when selecting and integrating IP. For example, with the number of IP cores in embedded SOC designs growing, the bus structures to handle them are becoming more complex and time-consuming to design. As a result, multiple processors are competing for memory resources, causing memory access problems. These are just some of the challenges facing designers today when selecting and integrating IP.
Read the entire article from Sonics, Inc. on SOCcentral.
SOC System Management IP Virtualizes SOC System Management
If we look back at the evolution of the PC architecture for direction, we discover virtualization. When the levels of complexity on the motherboard became overwhelming to manage, PCI decoupled all the functions and coordinated them through an independent system block. Now that software is becoming overwhelming, several companies are offering products that abstract and virtualize the PC software. Likewise, as the new SOC topologies are making it increasingly difficult to manage system functions, virtualization will play a role in SOCs.
Read the entire article from ChipStart on SOCcentral.
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SOCcentral news items about Selecting and Integrating IP |
| Altera Stratix V GX FPGAs Achieve PCIe Gen3 Compliance and Listing on PCI-SIG Integrators List (5/21/2013) |
| Imec and GlobalFoundries Collaborate to Advance High-Density Memory Technology (5/21/2013) |
| Fourth Multicore Challenge Now Open for Registration (5/20/2013) |
| QuickLogic Parallel Camera Interface for TI Sitara AM335x ARM Cortex-A8 Processors Supports Android Jelly Bean 4.1.2 OS (5/20/2013) |
| sureCore Receives SMART Award to Prototype Its Low-Power SRAM Technology (5/20/2013) |
| Synopsys DesignWare IP for PCI Express 3.0 Passes First PCI-SIG PCIe 3.0 Compliance Workshop (5/20/2013) |
| Test and Verification Solutions Expands Library of Verification IP (5/20/2013) |
| Xilinx Achieves PCI Express Compliance Across Its All Programmable 28-nm Devices (5/20/2013) |
| Ultra-Low Latency H.264 Video Encoding Now Available from CAST (5/16/2013) |
| New Power ISA 2.07 Now Available from Power.org (5/15/2013) |
| Altera to Acquire Enpirion (5/14/2013) |
| Chip Memory Technology Emerges from Stealth Mode to Reveal New Embedded NV Memory Solution (5/14/2013) |
| Elecard Releases New Version of Elecard ARM Codec SDK (5/14/2013) |
| TI Delivers ZigBee SOC with an ARM Cortex-M3 MCU (5/14/2013) |
| Energy-Efficient EFM32 Wonder Gecko with ARM Cortex-M4 and FPU Now Available (5/13/2013) |
| HiSilicon Technologies Tapes Out 50+ Million Instance ARM Processor-based SOC Using Synopsys IC Compiler (5/13/2013) |
| Management Day at DAC to Discuss the Trade-Offs Involved in Modern SOC Design (5/13/2013) |
| Si2 Celebrates Its 25th Anniversary with Complimentary Lunch and Evening Reception During DAC (5/13/2013) |
| UltraSoC Delivers Universal Debug IP to PMC-Sierra (5/13/2013) |
| eMemory Announces NeoFuse Anti-Fuse eNVM Technology (5/8/2013) |
| Broadcom Introduces Low-Power Processor SOC for Switch Control-Plane Applications (5/7/2013) |
| Broadcom Unveils Highly Integrated Processor SOC for 5G WiFi Enterprise Access Points (5/7/2013) |
| Cadence to Acquire Evatronix's IP Business (5/7/2013) |
| S3 Group Licenses Custom ADC and DAC Solutions to Avalent Technologies (5/7/2013) |
| STMicroelectronics and Quantenna Enter Strategic Licensing Agreement (5/7/2013) |
| Tanner EDA Joins ARM Connected Community (5/7/2013) |
| Intelbras Chooses DSP Group's XciteR Platform to Power IP Phones (5/6/2013) |
| AMD to Create Tailored Products Integrating Customer-Specific IP (5/2/2013) |
| Pixelworks Introduces Display Processor for Mainstream DLP Projectors (5/2/2013) |
| HCC Accelerates Embedded Projects with Online Rapid Customization Tool (4/30/2013) |
| MCU Market on Migration Path to 32-bit and ARM-based Devices (4/30/2013) |
| Sonics and ARM Enter Patent License Agreement and Broaden Technology Cooperation (4/30/2013) |
| STMicroelectronics Adds New Microcontroller to STM32F4 Series (4/30/2013) |
| Athena Introduces New Pipelined and Parallel-Pipelined Multi-Radix FFT/DFT IP Cores (4/29/2013) |
| CEVA Introduces First Software-Based Super-Resolution Technology for Low-Energy Mobile Applications (4/25/2013) |
| Digital Core Design New Fast and Configurable 8051 IP Core (4/25/2013) |
| Jumpstart and Explore Sensor Fusion Applications with TI's New Sensor Hub BoosterPack (4/24/2013) |
| NASA Selects Ridgetop Group to Develop Modular SiGe 130-nm Cell Library (4/24/2013) |
| ARM Releases Free Industry-Standard Development Tools for Its Embedded Linux Community (4/23/2013) |
| Chips&Media Announces New Generation HEVC Video Decoder (4/23/2013) |
| HDL Design House Introduces JESD204B PCS IP Core (4/23/2013) |
| Renesas Electronics Selects DMP's SMAPH-S 3D Graphics IP Core (4/23/2013) |
| S3 Group Announces Latest Release to its RF and Mixed-Signal IP Product Guide (4/23/2013) |
| STMicroelectronics Powers Advanced Generation of Smart IPTV Set-Top Boxes from NTT Plala (4/22/2013) |
| CEVA Introduces Android Multimedia Framework for Energy Efficient Multicore Systems (4/18/2013) |
| Imagination's PowerVR VXE Multi-Standard Video-Encoder IP Now Supports VP8 (4/18/2013) |
| Joe Costello Shares His Secrets for Communicating a Compelling Company Story (4/18/2013) |
| Andes Technology Unveils New Ultra-Efficient Processor Core for Low-Power Applications (4/17/2013) |
| ARM and Arteris Extend Partnership to Deliver Additional Interconnect Options (4/17/2013) |
| ARM Introduces New License Model for Big.Little Technology (4/17/2013) |
| Accellera Systems Initiative Announces Standard for Tracking Soft IP Use (4/16/2013) |
| Arasan Chip Systems Announces First SD 4.1 Total IP Solution (4/16/2013) |
| Flexras Technologies Enhances Wasga Compiler Partitioning Tool (4/16/2013) |
| Leadcore Adopts Hantro Video IP (4/16/2013) |
| Rockchip Leverages Arteris FlexNoC Interconnect IP for Next-Generation SOCs (4/16/2013) |
| S3 Group First to Market with 28-nm Power-Management IP Products (4/16/2013) |
| Altera Acquires TPACK to Expand OTN Solution Capabilities (4/15/2013) |
| Altera and AppliedMicro to Cooperate on Joint Solutions for High-Growth Data Center Market (4/15/2013) |
| Altera and TSMC Collaborate on 55-nm EmbFlash Process (4/15/2013) |
| Ambarella AmbaCast 8000 Platform Delivers New Capabilities for Video-Infrastructure Applications (4/15/2013) |
| Annual SoCIP Conference Opens for Registration (4/15/2013) |
| Dolphin Integration Introduces Complete IP Offering for Power-Metering Applications (4/15/2013) |
| Evatronix Enhances Its MIPI SLIMbus Device IP with New Customization Options (4/15/2013) |
| International System-on-Chip (SoC) Conference Calls for Speakers and Sponsors (4/15/2013) |
| LSI Introduces Axxia 4500 Family of ARM Technology-based Communication Processors to Accelerate Enterprise and Data Center Networks (4/15/2013) |
| Microsemi Achieves NIST Certification on EnforcIT Cryptography IP Cores for FPGA and ASIC Designs (4/15/2013) |
| Synopsys IC Validator Enables LG Electronics to Accelerate Manufacturing Compliance (4/15/2013) |
| TI Introduces New Tiva C Series ARM Cortex-M4 Microcontrollers (4/15/2013) |
| ARM Announces POP IP for Cortex-A50 Series Processors on TSMC 28-nm HPM and 16-nm FinFET Processes (4/9/2013) |
| Fujitsu Semiconductor ASIC Design for 2G/ 3G/ 4G Baseband Processor in Volume Production with Synopsys 28-nm MIPI M-PHY (4/9/2013) |
| Imperas Delivers ARM Cortex-A7 MPCore Processor Model with Integrated Software Development Environment (4/9/2013) |
| Altera Demonstrates 32-Gbps Transceiver with Leading-Edge 20-nm Device (4/8/2013) |
| intoPIX Launches New Ultra-Compact JPEG2000 FPGA IP Cores (4/8/2013) |
| Tata Elxsi Unveils HEVC Ultra HD (4K) Decoder for Smartphones, Tablets, Set-Top Boxes, Gaming Consoles and Other CE Devices (4/8/2013) |
| Xilinx Enables OEMs to Develop Smarter Broadcast Solutions with Availability of Its Real-Time Video Engine 2.1 (4/8/2013) |
| Xilinx Vivado Design Suite Accelerates Time-to-Integration and System-Level Design (4/8/2013) |
| Open-Silicon Extends its TSMC VCA Partnership to Include Israel (4/5/2013) |
| ARM and Cadence Partner to Implement First Cortex-A57 64-bit Processor on TSMC 16nm FinFET Process (4/4/2013) |
| Cryptography Research and StarChip Sign Patent License Agreement for DPA Countermeasures (4/4/2013) |
| Accellera Systems Initiative Launches Working Group to Standardize Interoperability of Multiple Language Verification Environments and Components (4/3/2013) |
| Xilinx Vivado Design Suite Accelerates Time to Integration and System-Level Design (4/3/2013) |
| Altis Semiconductor Introduces the Next Generation of Embedded CBRAM Technology (4/2/2013) |
| ARM and TSMC Tape-Out First ARM Cortex-A57 Processor on TSMC's 16-nm FinFET Technology (4/2/2013) |
| Digital Core Design Unveils New I2C Bus-Interface Core (4/2/2013) |
| GSA to Host 2013 GSA Silicon Summit (4/2/2013) |
| Ittiam Unveils a Full HD Low-Latency Streaming Solution with a Latency of less than 70ms (4/2/2013) |
| Real Time Logic Secures ASIC-Powered Devices M2M Applications (4/2/2013) |
| EDA Consortium Reports Revenue Increase for Q4 2012 (4/1/2013) |
| Sidense 1T-OTP NVM Qualified for Automotive High-Reliability Requirements on TSMC's BCD Process (4/1/2013) |
| Algo-Logic Systems Launches Second-Generation Ternary Search Engine Solutions for the New Tabula ABAX2 P-Series of 3PLDs (3/27/2013) |
| OCP-IP Releases OCP Debug Socket Specification 2.0 (3/26/2013) |
| Algotochip Becomes Tensilica Design Center Partner (3/25/2013) |
| ARM and Synopsys Collaborate to Deliver Optimized Reference Implementations for ARM Processors (3/25/2013) |
| Imagination's MIPS-based Multi-Threaded CPUs Push Performance to New Levels for Altair's New LTE Chipsets (3/25/2013) |
| INRIA and Kalray Strengthen Their Scientific Collaboration on the MPPA Manycore Processor and Parallel Computing (3/25/2013) |
| Microsemi Integrates Inicore Enhanced Reliability CAN IP into SmartFusion2 SoC FPGA (3/25/2013) |
| MorethanIP Releases First IP for 100GBase-CR4 and 100GBase-KR4 Applications (3/25/2013) |
| Sidense Qualifies 1T-OTP Non-Volatile Memory for MagnaChip 180-nm Mixed-Signal and HV CMOS Process (3/25/2013) |
| Truechip Solutions Partners with Avant Technology to Market Verification IP Products in Asia (3/25/2013) |
| TSMC Optimizing 16-nm FinFET Design Flows Using Imagination' PowerVR GPUs to Drive Mobile Performance (3/25/2013) |
| Cypress's PSoC 4 Architecture Delivers the Most-Flexible, Lowest-Power ARM Cortex-M0-Based Devices for Embedded Designs (3/20/2013) |
| Beken Licenses CEVA Bluetooth 2.1+EDR and 4.0 IP for Low-Power Bluetooth Product Families (3/19/2013) |
| Global Unichip Unveils New 28-nm Data Converter IP Family (3/19/2013) |
| Tensilica Joins HSA Foundation to Help Establish Standards for Embedded Heterogeneous Computing (3/19/2013) |
| Xilinx Extends its Zynq-7000 All Programmable SoC Family to Combine the Highest-Performance ARM Processor-based Analytics, Control and Signal Processing (3/19/2013) |
| Arasan Chip Systems Announces New Channel Partner in India (3/18/2013) |
| Bluespec Introduces High-Speed Verification and Hybrid Prototyping Solution for RTL IP (3/18/2013) |
| Chips&Media Extends CODA9 Series with AVS+ Chinese New Video Standard (3/18/2013) |
| Ittiam Systems Announces Availability and Software Licensing of HEVC (H.265) Video Encoder and Decoder (3/18/2013) |
| Tektronix Demonstrates MIPI Alliance M-PHY Test Solution with Synopsys Silicon-Proven HS-Gear3 M-PHY IP (3/18/2013) |
| CAST Issues 8051 IP Core License to Ensphere Solutions (3/12/2013) |
| HDL Design House Announces PCS IP Core (3/12/2013) |
| Cadence Announces First Commercially Available Design IP and Verification IP for Mobile PCI Express (3/11/2013) |
| Cadence to Acquire Tensilica (3/11/2013) |
| Carbon Expands Embedded Systems Offerings with Performance Analysis Kit Featuring the ARM Cortex-R7 Processor (3/11/2013) |
| Digital Core Design Announces DuART tiny UART IP Core (3/11/2013) |
| Renesas Electronics Develops Multi-Format Video Codec Hardware IP that Supports Low-Delay Processing (3/11/2013) |
| STMicroelectronics Re-Asserts Its MEMS Patent Leadership and Requests an ITC Investigation of InvenSense (3/11/2013) |
| Kilopass Receives $8 Million Funding to Expand Technology Roadmap (3/7/2013) |
| Carbon Announces Carbon Performance Analysis Kit Featuring the ARM Cortex-R7 (3/5/2013) |
| Dongbu HiTek and Cortus to Develop Joint Platform Solution for the Microcontroller Market (3/5/2013) |
| Avant Technology to Represent Recore Systems' IP Products in Asia (3/4/2013) |
| Dolphin Integration Announces Availability SpRAM Generator for TSMC 55 LP Process (3/4/2013) |
| MegaChips Completes Design Center Agreement with Tensilica (3/4/2013) |
| Spansion and UMC Announce Joint Technology Development and Licensing Agreement (3/4/2013) |
| Toshiba Visconti3 Adds Dual-Core ARM Cortex-A9 CPU that Enhances Image-Recognition Performance (3/4/2013) |
| Xilinx Solutions Target Growing ASIC and ASSP Gaps for Next-Generation Smarter Networks and Data Centers (3/4/2013) |
| ARM Announces mbed v2.0 and Releases Open-Source SDK and Development Board HDK (3/1/2013) |
| ARM Mali GPUs Submitted for OpenGL ES 3.0 Conformance (3/1/2013) |
| Arasan Announces eMMC 5.0 Total IP Solution (2/28/2013) |
| AM3D Audio Enhancement Ported to Tensilica's HiFi Audio DSPs (2/27/2013) |
| Cadence Rolls Out 2013 CDNLive User Conferences (2/27/2013) |
| Freescale and ARM Extend Relationship with Cortex-A50 Processor License for Future i.MX and QorIQ Products (2/27/2013) |
| Freescale Introduces Kinetis KL02 ARM-Based Microcontroller (2/27/2013) |
| VLSI Plus Offers Multiple Video Source MIPI CSI2 Transmitter IP Core (2/27/2013) |
| Altera Introduces FPGA-Based HSR/PRP Reference Design Targeting Smart-Grid Automation Equipment (2/26/2013) |
| CSR Licenses aptX Low-Latency Codec to Mad Catz for New Family of Bluetooth Wireless Gaming Headsets (2/26/2013) |
| LTE and LTE Advanced Baseband Processing Get Performance Boost from MIPS Multi-Threaded Cores (2/26/2013) |
| MIPS Processor Cores Power Ceragon Networks' Next-Generation Multicore Packet SDR (2/26/2013) |
| Newport Media Announces Wi-Fi SOC Incorporating a Cortus APS3 Processor (2/26/2013) |
| Nextchip Selects Cortus APS5 for Automotive and Security Applications (2/26/2013) |
| PowerVR G6100 Series6 Rogue Core Enables Mass-Market OpenGL ES3.0 (2/26/2013) |
| Socle Technology Now Offers Arteris FlexNoC Platform (2/26/2013) |
| ASOCS and CMCC Team Deliver Mass-Market High-Capacity, Commercially Viable C-RAN Solutions (2/25/2013) |
| Cavium Demonstrates Mobile Infrastructure Solutions for Next Generation Radio Access, Core Network, and Wireless Display Manufacturers (2/25/2013) |
| DSP Group License CEVA Audio DSP for HDClear Voice-Enhancement Solution
(2/25/2013) |
| Huawei HiSilicon Licenses Full Range of Tensilica IP Cores (2/25/2013) |
| Imec and Target Collaborate Multi-Standard Low-Power LDPC Engine for Multi-Gbps Wireless Communication (2/25/2013) |
| LG U+ Selects Cavium's OCTEON Fusion for Its LTE Small-Cell Roll-Outs (2/25/2013) |
| Qualcomm Snapdragon 800 Processor First to Use TSMC's 28HPM Advanced Process Technology (2/25/2013) |
| Rambus Unveils Binary Pixel Technology for Dramatically Improved Image Quality in Mobile Devices (2/25/2013) |
| Silicon Image MHL Technology Featured on New MediaTek Quad-Core Mobile Computing Reference Platform (2/25/2013) |
| Xilinx and TEKTELIC Reduce Cellular Radio Infrastructure Development Time with Scalable IP and High-Performance Transceiver (2/22/2013) |
| ARM and Synopsys Collaborate to Optimize ARM Mali GPU 20-nm Implementation (2/21/2013) |
| GlobalFoundries Offers Enhanced 55-nm CMOS Logic Process with ARM Next-Generation Memory and Logic IP Support for Low Voltage (2/21/2013) |
| IAR Systems Supports the Infineon XMC1000 ARM Cortex-M0 Microcontrollers (2/21/2013) |
| SimpLight Achieves First LTE Modem Silicon Success Using Tensilica's Complete Atlas Reference Platform (2/21/2013) |
| STMicroelectronics Multicore MCUs Enable Functional Safety Compliance in Automotive Systems (2/21/2013) |
| Xilinx Launches Fully Adaptive Gbps-Class Point-to-Point Microwave Modem IP for Backhaul Applications (2/21/2013) |
| HIMA Licenses ColdFire V4 Technology from IPextreme (2/20/2013) |
| Imagination Achieves OpenGL ES 3.0 Conformance for PowerVR Series6 Cores (2/20/2013) |
| Latest STM32 ARM Cortex Devices Deliver Leading Performance and Graphics Features (2/20/2013) |
| Rambus and LSI Corporation Sign Patent License Agreement (2/20/2013) |
| CAST Adds Multicast and AXI to UDP/IP Core for Streaming Media Systems (2/19/2013) |
| CEVA and Mindspeed Extend Relationship to Address LTE-Advanced Small Cells (2/19/2013) |
| CEVA and Sensory Partner to Deliver Low-Power Voice-Activation Solution Based on CEVA-TeakLite-4 DSP Platform (2/19/2013) |
| CEVA Introduces MUST Multicore System Technology, Adds Vector Floating-point Capabilities for CEVA-XC DSP Architecture Framework (2/19/2013) |
| New mimoOn Library for Tensilica's Baseband DSP IP Cores Speeds LTE and LTE-Advanced Chip Designs (2/19/2013) |
| Optimized Port of Sensory's TrulyHandsfree 3.0 Speaker Verification and Speaker Identification Available on Tensilica HiFi Audio/Voice DSPs (2/19/2013) |
| Creonic Announces WiGig (802.11ad) LDPC Decoder IP (2/18/2013) |
| Nuvoton Technology Debuts NUC123 Family of 32-bit Cortex-M0 MCUs (2/18/2013) |
| S3 Group Launches 10 New Silicon-Proven IP Cores (2/18/2013) |
| Vitesse Introduces IP Cores for Consumer, Enterprise and Industrial Applications (2/18/2013) |
| Bwave and Ubiso to Demonstrate Licensable Multi-Standard DVB-T2 DTV Demodulation IP Subsystem Based on Tensilica's ConnX BBE16 DSP (2/15/2013) |
| NXP HD Voice Processing Smartphone Software Now Available for Tensilica's HiFi Audio/Voice DSPs (2/14/2013) |
| Renesas Mobile Introduces Quad-Core ARM Cortex-A15/ Cortex-A7 CPU-Based Communication Processor with Integrated LTE Cat-4 Modem (2/14/2013) |
| RFEL Launches Video-Image-Stabilization IP Core (2/14/2013) |
| StarChip Announces Sampling of Its SCF670H SIM Controller to Tackle the 4G/LTE Market (2/13/2013) |
| Tensilica and Acoustic Technologies Extend Partnership to Deliver Complete Wideband HD Voice Processing Solution (2/13/2013) |
| Actions Semiconductor Licenses Arteris FlexNoC Interconnect IP for Multimedia Application Processors (2/12/2013) |
| Almalence Ports Optimized Image Processing Software onto Tensilica's New IVP Imaging/ Video DSP (2/12/2013) |
| DVCon 2013 Announces Keynote, Final Program, Executive Panel Lineup (2/12/2013) |
| IDT Announces High-Performance Data-Compression IP for 3G and 4G Wireless-Infrastructure Applications (2/12/2013) |
| Irida Labs and Tensilica Partner for Computer Vision Applications on Tensilica's New IVP Imaging/ Video DSP (2/12/2013) |
| Morpho and Tensilica Partner for Image Processing Solutions for Mobile Devices (2/12/2013) |
| Tensilica Unveils IVP Imaging/ Video DSP IP Core for Mobile Handsets, DTV, Automotive and Computer-Vision Applications (2/12/2013) |
| Athena Groups Breaks 200-µs Latency Barrier for RSA-2048 Operations (2/7/2013) |
| Cadence Expands IP Portfolio with Agreement to Acquire Cosmic Circuits (2/7/2013) |
| GSA Silicon Summit to Explore More-than-More Movement (2/7/2013) |
| LeadingUI Chooses Cortus APS1 Processor for Touchscreen Applications (2/7/2013) |
| Pixelworks Selects Uniquify's DDR Memory-Controller Subsystem IP (2/7/2013) |
| Real Intent to Sponsor Design Verification Club Silicon Valley Event 2013 on Valentine's Day (2/7/2013) |
| Analog Bits IP Now Shipping in Microsemi's SmartFusion2 SoC FPGAs (2/6/2013) |
| EDA Consortium Outlines CEO Forecast and Industry Vision Event on March 14 (2/5/2013) |
| GlobalFoundries and Cyclos Semiconductor Partner to Develop High-Performance, Low-Power ARM Cortex-A15 Processors Using Resonant-Clock-Mesh Technology (2/5/2013) |
| GlobalFoundries Details 14nm-XM FinFET Technology Performance, Power and Area Efficiency with a Dual-core Cortex-A9 Processor Implementation (2/5/2013) |
| GlobalFoundries to Offer Adapteva's Processor IP for 28-nm SOC Designs (2/5/2013) |
| Phison Licenses Tensilica's Dataplane Processor (DPU) for NAND Flash Memory Controllers and SSD Applications (2/5/2013) |
| Rambus and GlobalFoundries Collaborate to Develop IP Portfolio for 14nm-XM FinFET Process Technology (2/5/2013) |
| Synopsys and GlobalFoundries Partner to Provide Comprehensive Design Environment for Foundry's 14-nm-XM FinFET Offering (2/5/2013) |
| Imagination Submits PowerVR Series6 Cores for OpenGL ES 3.0 Conformance (2/4/2013) |
| TU Dresden Realized 28-nm Low-Power Test Chip with Tensilica Processor and RacyICs Power Management in GlobalFoundries Process (2/4/2013) |
| Cadence Releases Verification IP for USB SuperSpeed Inter-Chip Specification (1/31/2013) |
| Daou InCube to Offer Design Platforms based on Cortus Processors (1/31/2013) |
| Digital Core Design Introduces Local Interconnect Network IP Core (1/31/2013) |
| Microsemi Introduces SmartFusion2 SoC FPGA Starter Kits to Speed Product-Development Efforts (1/31/2013) |
| Imagination Technologies Selects Synopsys as Advanced Verification Technology Partner (1/30/2013) |
| Kilopass NVM IP Achieves JEDEC Qualification on High-Demand SMIC 65/55/40-nm Processes (1/30/2013) |
| Recore Systems Joins Constellations Program; Adds DSP IP to Constellations Semiconductor IP Center (1/30/2013) |
| Freescale Semiconductor Partners with IAR Systems to Reach New Performance Levels (1/29/2013) |
| GUC Successfully Validates a 28-nm GPU/CPU Platform (1/29/2013) |
| Intilop Delivers True Ultra-Low-Latency 10G NIC with Its 5th Generation 76-ns TCP and UDP Off-Load Technology (1/29/2013) |
| MegaChips Licenses Arteris FlexNoC Fabric IP for Next-Generation Imaging SOCs (1/29/2013) |
| New 32-bit BA25 Application Processor Adds More Performance to Royalty-Free BA2x Family (1/29/2013) |
| Oasys Design Systems Joins the TSMC Soft-IP Alliance Program (1/29/2013) |
| Posedge Launches 2x2 MIMO WLAN MAC and Baseband IP (1/29/2013) |
| Synopsys Announces Energy-Efficient 28-nm PCI Express 3.0 PHY with Support for 10GBASE-KR (1/29/2013) |
| Evatronix Adds Scaling Capabilities to its PANTA DP20 Display Processor (1/28/2013) |
| intoPIX Launches New Compact JPEG2000 Encoder and Decoder FPGA IP Cores (1/28/2013) |
| Phoenix Systems Ports Phoenix-RTOS to EnSilica's eSi-RISC Processor Family (1/28/2013) |
| Rambus Introduces R+ LPDDR3 Memory Architecture Solution (1/28/2013) |
| Real Intent Delivers Next Release of Meridian Constraints for Advanced Sign-Off of SOC Designs (1/28/2013) |
| Faraday and UMC Deliver 300-Million-Gate 40-nm Customer SOC (1/22/2013) |
| MoSys Announces Renesas Electronics Support of GigaChip Interface for Chip-to-Chip Communications (1/22/2013) |
| New Release of Cadence Incisive Platform Doubles Productivity of SOC Verification (1/22/2013) |
| Open-Silicon Implements Arteris FlexNoC Interconnect IP in ARM Cortex-A9 ASIC (1/22/2013) |
| Synopsys Accelerates Adoption of FinFET Technology with Delivery of Production-Proven Design Tools and IP (1/22/2013) |
| e2v Releases PC8378x PowerQUICC II Pro Communications Processors for Extended-Reliability Applications (1/21/2013) |
| eMemory's NeoEE IP Qualified for 2.4-GHz RF Product Application (1/21/2013) |
| Freescale Boosts Verification Productivity with Synopsys Verification IP (1/21/2013) |
| Mentor Graphics Delivers Emulation Solutions for Verification of ARM Cortex-A9 MPCore-based Products (1/21/2013) |
| Elliptic Technologies Introduces New Multi-Protocol Security Engine to Support Home/Office Networking and LTE Small-Cell Applications (1/17/2013) |
| HDL Design House Appoints Applied Micro Systems to Offer IP cores and SOC Services in the UK and Ireland (1/17/2013) |
| Infineon's New XMC1000 Industrial Microcontroller Family Delivers 32-bit Performance at 8-bit Prices (1/17/2013) |
| ALi Integrates Cryptography Research CryptoFirewall Security Core into Next Generation SOC Solutions (1/15/2013) |
| MediaTek Extends Licensing Partnership with Imagination to TV Market (1/15/2013) |
| Atmel Expands ARM Cortex-M4-based Flash Microcontroller Family (1/14/2013) |
| Archband Labs Achieves SMIC Qualified 96dB Hi-Fi Audio Codec IP in 65-nm LL Process (1/10/2013) |
| IPextreme Announces Atrenta as First EDA Company to Join Constellations (1/9/2013) |
| Analog Bits Uses Tanner EDA Schematic Capture and Layout Tools in Migration from 28nm to 20nm (1/8/2013) |
| ARM and Broadcom Extend Relationship with ARMv7 and ARMv8 Architecture Licenses (1/8/2013) |
| Digital Blocks Extends I2C Controller IP Core Family (1/8/2013) |
| Imagination Adds New Extended API Features to PowerVR Series5XT (SGX) GPUs (1/8/2013) |
| Vivante Joins GENIVI Alliance Bringing OpenGL ES 3.0 and OpenCL to Automotive Platforms (1/8/2013) |
| CEVA Partners with iOnRoad to Deliver Personal Driving-Assistance Technology with CEVA-MM3101 Platform (1/7/2013) |
| DarbeeVision Licenses HDMI Video-Processor Design to Lumagen (1/7/2013) |
| EDA Consortium Reports Revenue Increase for Q3 2012 (1/7/2013) |
| Microsemi and Intrinsic-ID Deliver Integrated Security Solutions for Government Applications (1/7/2013) |
| MIPS-Based SOC from Ingenic Sets New Performance Point for Power-Efficient and Affordable Devices (1/7/2013) |
| Rambus Unveils Imerz, an End-to-End Interactive Multi-Media Platform (1/7/2013) |
| Waves MaxxAudio Sound-Enhancement Technology Now Available for Tensilica HiFi Audio DSP Cores (1/7/2013) |
| Xylon Announces logiSPI SPI-to-AXI4 Controller Bridge IP Core for Xilinx Zynq-7000 AP SoC and FPGAs (1/7/2013) |
| YoYo Games and MIPS Release Free Android Game Development Platform Exclusively for MIPS-Based Devices (1/7/2013) |
| CEVA Introduces Comprehensive Computer Vision Library Optimized for CEVA-MM3101 Imaging and Vision Platform (1/3/2013) |
| Digital Core Design Introduces DQSPI Quad-Performance SPI (1/3/2013) |
| Tensilica Introduces the Smallest, Lowest Power DSP IP Core for Always-Listening Voice Trigger and Voice Recognition (1/3/2013) |
| Eclipse IDE Now Available for Users of IAR Embedded Workbench for ARM (1/2/2013) |
| M31 Technology Joins TSMC IP Alliance (12/19/2012) |
| HDL Design House MIPI M-PHY and D-PHY Solutions Available in 40nm and 65nm (12/18/2012) |
| Sitara ARM Processors Launch Support for Android 4.1.2 Jelly Bean (12/18/2012) |
| Vivante Shipping Smallest and Lowest-Power OpenGL ES 3.0 IP Core (12/18/2012) |
| Elliptic Technologies Selects Synopsys' Discovery VIP for ARM AMBA Interconnect for Verification of Its Security Systems (12/17/2012) |
| Alizem COTS Motor-Control Software IP for Servo-Drive Applications Receives Altera AMPP Certification (12/12/2012) |
| Altera and ARM Announce FPGA-Adaptive Embedded Software Toolkit (12/12/2012) |
| Altera Ships Its First SOC Devices (12/12/2012) |
| CEVA and Orca Partner to Deliver Complete Bluetooth 4.0 Reference Design (12/12/2012) |
| CEVA Offers MIPS $90 Million for Its Operating Business (12/12/2012) |
| ReFLEX CES Introduces Aurora-Like IP Cores (12/12/2012) |
| Xylon Showcases 3D Graphics Engine for Xilinx Zynq-7000 All Programmable SoC (12/12/2012) |
| Arasan Expands Ethernet Portfolio by Adding Audio Video Bridging (12/10/2012) |
| Creonic Announces MMSE MIMO Detector IP Core (12/10/2012) |
| Cypress Extends TrueTouch Gen4 Touchscreen Controller Line (12/10/2012) |
| Dolphin Integration Achieves 0.84pA/bit in SpRAM at the 90-nm uLL Embedded Flash Process (12/10/2012) |
| HDL Design House Introduces MIPI CSI-2 Transmitter IP Core (12/10/2012) |
| IAR Systems Extends Development Tools Offering with a Special Edition for the Smallest ARM Cores (12/10/2012) |
| Mentor Embedded Accelerates High-Performance Signal- and Image-Processing Application Development with Support for MATLAB and ARM Platforms (12/10/2012) |
| SuVolta Announces Circuit-level Performance and Power Advantages of DDC Technology (12/10/2012) |
| Autotalks Deploys Sonics Technology for Vehicle-to-Vehicle Communication (12/5/2012) |
| Atrenta Ships 5.0 Release of SpyGlass Platform (12/4/2012) |
| Kilopass NVM IP Proves Manufacturability and Process Control Tolerance on TSMC's 20-nm CMOS-Process Test Chips (12/4/2012) |
| GUC Delivers 28nm DDR3-2133/LPDDR2 Combo IP (12/3/2012) |
| MagnaChip Engages with eMemory in Joint Development of 0.18-µm EEPROM IP (12/3/2012) |
| PLDA and GUC Announce Successful PCIe Gen 3 Controller and PHY Combination on TSMC's 28-nm HPM Process Technology (12/3/2012) |
| RivieraWaves Achieves 802.11n Certification and Announces Wi-Fi 802.11ac Silicon IP (12/3/2012) |
| Sonics Provides Preliminary Results of Network-on-Chip Survey (12/3/2012) |
| Cadence Announces Availability of First Design IP and Verification IP for Ethernet-Based Automotive Connectivity (11/27/2012) |
| CAST Offers H.264 High-Profile Encoder IP Core for FPGAs and ASICs (11/27/2012) |
| Noesis Technologies Unveils ITU-T G.729A-Compliant Voice Codec Hardware Accelerator (11/27/2012) |
| Tensilica and mimoOn Partner to Provide the Comprehensive LTE and LTE-Advanced Hardware-Software PHY IP Solution (11/27/2012) |
| Cosmic Circuits Announces Silicon Proven MIPI M-PHY in Multiple 28-nm Flavors (11/26/2012) |
| Dolphin Integration Introduces a New Generation of SpRAM at 55nm (11/26/2012) |
| HDL Design House Announces MIPI DSI (Controller + D-PHY) IP Solutions (11/26/2012) |
| CEVA Joins Heterogeneous System Architecture (HSA) Foundation (11/20/2012) |
| Kilopass XPM IP Provides Non-Volatile Memory in IBM 65-nm LPE Process for Portable Devices (11/20/2012) |
| MIPS Technologies Announces Receipt of Unsolicited Proposal from CEVA (11/20/2012) |
| Sonics Participates in TSMC's Soft IP Kit 2.0 Beta Program (11/20/2012) |
| STMicroelectronics Extends Position in Semiconductors for Smarter Embedded Electronics (11/20/2012) |
| Altera Quartus II 12.1 Accelerates System Development with Enhanced High-Level Design Flows (11/19/2012) |
| CEVA and DiMAGIC Partner to Integrate Adaptive Beam-Forming with CEVA-TeakLite Family of DSPs (11/19/2012) |
| GOEPEL electronic Introduces ChipVORX Prototype Instruments for Bit-Error-Rate Tests (11/19/2012) |
| PLDA Announces Integration of Its PCIe 2.0 Controller with the AMBA AXI interface in Microsemi's SmartFusion2 SoC FPGA (11/19/2012) |
| Xtendwave Selects TowerJazz to Manufacture Next-Generation WWVB Atomic Timekeeping-Signal Receiver Products (11/19/2012) |
| ASACA Releases a New Range of Broadcast Servers Based on intoPIX HD JPEG2000 Technology (11/15/2012) |
| Imagination Extends PowerVR Series 6 Family with G6630 6-Cluster GPU (11/15/2012) |
| RFEL to Launch Family of Video-Processing Cores (11/15/2012) |
| Think Silicon GPUs Power Latest Dialog Semiconductor VOIP Chipsets (11/15/2012) |
| Altera and Northwest Logic Develop RLDRAM 3 Memory-Interface Solution (11/13/2012) |
| Alizem Releases its COTS Motor Control Software IP for Servo-Drive Applications on Altera FPGAs (11/12/2012) |
| Altera Motor-Control Development Framework Delivers Scalable Performance and Flexibility (11/12/2012) |
| Altera Simplifies Industrial Ethernet Design for Factory Automation Systems (11/12/2012) |
| Dolphin Integration's Audio Codec Passes TSMC IP9000 Level-4 40-nm Low-Power Certification (11/9/2012) |
| Altera's Functional Safety Data Package for Industrial Applications Accelerates Design Time and Reduces Certification Risks (11/7/2012) |
| DMP's PICA200 Lite 3D Graphics IP Core Adopted for OLYMPUS PEN Lite E-PL5.OLYMPUS PEN mini E-PM2 (11/6/2012) |
| Fujitsu Expands Line-Up of 32-bit General-Purpose Microcontrollers with New Products Built with Latest ARM Cores (11/6/2012) |
| Imagination Technologies Acquires MIPS Technologies (11/6/2012) |
| JEDEC and the Open NAND Flash Interface Workgroup Publish NAND Flash Interface Interoperability Standard (11/6/2012) |
| Mentor Graphics New Tessent IJTAG Product Automates IP Test and Debug Integration in Large SOC Designs (11/6/2012) |
| X-FAB and Anvo-Systems Dresden Cooperate to Provide High-Speed Non-Volatile Memory Solutions (11/6/2012) |
| Evatronix SA Selects MunEDA Tool Suite WiCkeD (11/5/2012) |
| GOEPEL electronic Introduces In-System Emulation Test for Infineon TriCore Architecture (11/5/2012) |
| RFEL Makes FPGA Performance Available to ARM Software Developers (11/5/2012) |
| StreamDSP Announces Update to Its sFPDP IP Core, Adding Support for 28-nm Devices from Xilinx and Altera (11/5/2012) |
| eSilicon and ARM Sign Multi-Year IP Agreement (11/1/2012) |
| LG Electronics Selects Uniquify's DDR Memory Subsystems IP for Latest SOC Design (11/1/2012) |
| Access Network Technology Licenses Arteris Chip-to-Chip (C2C) Interconnect IP (10/31/2012) |
| Altera Introduces Serial RapidIO Gen2 MegaCore IP (10/31/2012) |
| Cortus Releases the Smallest 32-bit Microcontroller IP Core (10/31/2012) |
| Digital Core Design Introduces Powerful Tiny 8-bit CPU (10/31/2012) |
| Elliptic Technologies Delivers Hardware-Assisted Premium Content Protection on Mobile and Home Entertainment Devices (10/31/2012) |
| Forte Rolls Out Latest Version of High-Level Synthesis Software (10/31/2012) |
| Kilopass Non Volatile Memory XPM IP Core Wins Accelerometer Sensor Design (10/31/2012) |
| Synopsys Extends Support for ARM AMBA Protocol Verification with New Performance Checker for AMBA 4 AXI4 (10/31/2012) |
| Xilinx Zynq-7000 All Programmable SoC Accelerates the Development of Trusted Systems (10/31/2012) |
| ARM Launches Cortex-A50 Series (10/30/2012) |
| Arteris FlexNoC Interconnect IP Licensed by Renesas Electronics Europe for Industrial SOCs (10/30/2012) |
| Atrenta and TSMC Announce SpyGlass IP Kit 2.0 Availability (10/30/2012) |
| STMicroelectronics to Spearhead Deployment of the ARM Cortex-A57 Processor for Next-Generation ASIC Solutions (10/30/2012) |
| CEVA Taps Inomize as Approved Design Center (10/29/2012) |
| Dolphin Integration's IP Offerings Support TSMC's Low-Leakage Devices on 180-nm eLL Process (10/29/2012) |
| HiSilicon Joins Linaro as Core Member (10/29/2012) |
| Imperas and OVP Provide ARM Cortex-A15 and Cortex-R4 Fast Processor Models (10/29/2012) |
| Samplify's New APAX IP Core Accelerates Memory, I/O, and Storage Throughput Up to 8X (10/29/2012) |
| Xilinx Announces Defense-Grade 7 Series FPGAs and Zynq-7000 All Programmable SoCs with Fourth-Generation Secure Capabilities (10/29/2012) |
| Blue Pearl Joins ARM Connected Community (10/24/2012) |
| Breker Verification Systems Adds Support for Multi-Processor SOCs (10/24/2012) |
| CEVA Partners with Rubidium to Deliver Speech-Processing Solutions Based on CEVA-TeakLite DSPs (10/24/2012) |
| PLDA Introduces QuickUDP, a 10G UDP Hardware-Stack IP for FPGAs (10/23/2012) |
| Renesas Electronics Unveils Next-Generation Microcontroller and Microprocessor Roadmap (10/23/2012) |
| Sonics Unveils Next-Generation SonicsGN (10/23/2012) |
| VLSI Plus Announces an FPGA Version of Its 64-bit Second-Generation MIPI CSI2 Receiver (10/23/2012) |
| CogniVue Unveils Next-Generation APEX Technology (10/22/2012) |
| IntelliProp Announces Availability of SATA RAID IP Core (10/22/2012) |
| Logic Bank Offers Design Services Based on Cortus 32-bit Processor Cores and Firmware (10/22/2012) |
| Analog Bits Completes Tape-Out of Mixed-Signal IP to TSMC's 20-nm HKMG Process (10/18/2012) |
| Uniquify Combines Design, IP Expertise to Deliver Low-Power, Low-Cost 10Gb Ethernet Controller to Tehuti Networks (10/18/2012) |
| Intrinsic-ID Launches Cloud Security Application Using Electronic Fingerprint (10/17/2012) |
| Moortec Semiconductor Announces Embedded PVT Die-Sensing IP for Deep Submicron Technologies (10/17/2012) |
| SatixFy Licenses CEVA-XC DSP for Broadband Satellite Applications (10/17/2012) |
| XMOS Launches New Tools and IP for Embedded Applications (10/17/2012) |
| Algotochip Joins ARM Connected Community (10/16/2012) |
| Carbon Design Systems Opens Office in Austin, Texas (10/16/2012) |
| IntegrIT's Wideband Acoustic Echo Canceller Now Available on Tensilica's HiFi Audio/Voice DSP (10/16/2012) |
| IntelliProp Announces Production Availability of AHCI-Compliant SATA Host Core (10/16/2012) |
| Cosmic Circuits and GDA Technologies Announce Availability of MIPI UniPro Solution (10/15/2012) |
| ARM Announces POP IP Technology for Mali-T600 Series GPUs (10/11/2012) |
| Inicore Introduces VME Slave Module Silicon IP Core (10/11/2012) |
| Kilopass Technology's Next-Generation Gusto-2 Targets Instant-On Mobile Devices (10/11/2012) |
| ARM Announces New High-Performance System IP to Address Demand for Energy-Efficient Many-Core Solutions for Enterprise Market (10/10/2012) |
| CEVA and NXP Software Partner to Deliver Enhanced HD Voice-Processing Solution Based on the CEVA-TeakLite-4 DSP (10/9/2012) |
| Freescale Announces Sub-Gigahertz Wireless Microcontroller Using Energy-Efficient 32-bit Processor Core (10/9/2012) |
| Freescale Enables Cost-Effective Meters Built on the ARM Cortex-M0+ Core (10/9/2012) |
| HDL Design House Adds New Sales Representative for China (10/9/2012) |
| Hisense Picks Tensilica HiFi Audio/Voice DSP and Software Codecs for DTVs (10/9/2012) |
| Moortec Semiconductor Signs Representative Agreement with ChipStart (10/9/2012) |
| SELEX to Use Intrinsic-ID's Security IP (10/4/2012) |
| Barco Silex's JPEG 2000 High-Frame-Rate Decoder Powers USL's Integrated Media Block (10/3/2012) |
| Cosmic Circuits Announces Availability of DigRFv4 Solution (10/3/2012) |
| MegaChips Selects Tensilica's HiFi Audio/Voice DSP for Consumer Products Designs (10/3/2012) |
| Si2 Announces Member Demonstrations at the 17th Si2 Conference (10/3/2012) |
| DTS Expands Enhanced Audio Offerings Available on Tensilica HiFi Audio/Voice DSP Cores (10/2/2012) |
| EDA Consortium Reports Revenue Increase for Q2 2012 (10/2/2012) |
| Open-Silicon Uses Synopsys IC Compiler to Achieve 1.3GHz on Quad-Core ARM Cortex-A9 MPCore Processor (10/2/2012) |
| Memoir Systems' Renaissance 4X Delivers Significant Memory Performance and Density Advantages (10/1/2012) |
| eMemory Introduces New NeoMTP Technology (9/27/2012) |
| IP Cores Announces Reed-Solomon Codec Supporting the IEEE 802.3bj Draft (9/25/2012) |
| Microtronix Announces Link Alignment Support for Medium and Full Camera Link IP Core Configurations (9/25/2012) |
| Beijing Nufront Licenses Latest ARM Cortex-A15 Processor and Mali-T658 GPU Technology (9/24/2012) |
| New Synopsys DesignWare UniPro Controller IP Streamlines Development of Storage, Camera and Display Interfaces (9/24/2012) |
| GlobalFoundries Unveils FinFET Transistor Architecture Optimized for Next-Generation Mobile Devices (9/20/2012) |
| Hitachi Selects Synopsys' Discovery Verification IP for ARM AMBA Interconnect for Verification of Storage Systems (9/19/2012) |
| Sunplus Shipping New Home Entertainment SOCs Powered by the CEVA-TeakLite-III Audio DSP in Volume (9/19/2012) |
| Kawasaki Microelectronics Achieves First-Silicon Success with Mixel's MIPI and MIPI/LVDS Unified Solutions (9/18/2012) |
| Kilopass Announces Technology to Quadruple Memory Capacity for Embedding Non-Volatile Data in SOC Products (9/18/2012) |
| Novocell Semiconductor Announces NVM IP Tape-Out at Trusted Foundry 32nm (9/18/2012) |
| Synopsys Announces DesignWare DDR4 Memory Interface IP (9/18/2012) |
| Cortus APS3 Processor Deployed in Selected Discretix CryptoCell Security Platforms (9/17/2012) |
| Xilinx Acquires Modesat Communications (9/17/2012) |
| Altera Expands Its OTN Portfolio with a Single-Chip 100G Muxponder Solution (9/13/2012) |
| CEVA Makes Strategic Equity Investment in Antcor, a Provider of Software-Based Wi-Fi IP (9/12/2012) |
| Samsung Invests $4 Million in Carbon Design Systems (9/12/2012) |
| intoPIX JPEG2000 Technology Selected for Integration in Visual Unity's New 4K Gateway Product (9/11/2012) |
| Sidense Licenses 1T-OTP to Exar (9/11/2012) |
| Freescale Qorivva Microcontroller Receives ISO 26262 Functional-Safety-Standard Certification (9/6/2012) |
| Xilinx and Barco Silex Ease Video-Over-IP Development with Launch of All Programmable Solutions and Design Services (9/6/2012) |
| Xilinx and OmniTek Launch the Era of All Programmable SoCs for Broadcast Equipment Makers (9/6/2012) |
| Cadence DDR4 Design IP Solutions Now Proven in 28-nm Silicon (9/4/2012) |
| Carbon and Arteris Simplify SOC Optimization (9/4/2012) |
| Digital Blocks Extends the DB9000 TFT LCD Controller IP Core Family with Support for QFHD LCD Panels (9/4/2012) |
| Innovative Logic Demonstrates USB3.0 SuperSpeed IP Using Spartan FPGA and TI USB3.0 PHY (9/4/2012) |
| Sigma Designs Announces HiDTV Pro-UXL for Smart TVs (9/4/2012) |
| Allegro DVT Annouces the HEVC Hardware Decoder IP (9/3/2012) |
| Arteris Joins HSA Foundation (9/3/2012) |
| CSR Debuts aptX Low-Latency Codec for Synchronized Audio and Video (9/3/2012) |
| PLDA Announces XpressV7LP Low-Profile PCIe FPGA Design Kit Based on Xilinx Virtex-7 FPGA (8/30/2012) |
| Sonics Joins Heterogeneous System Architecture Foundation (8/30/2012) |
| Evatronix and M31 Technology Introduce a USB-IF Certified Complete SuperSpeed USB 3.0 IP (8/29/2012) |
| Open-Silicon Announces Availability of Ethernet IP Co-developed with CoMira Solutions (8/29/2012) |
| ARM and Synopsys Expand Collaboration for ARM Technology-based SOCs (8/28/2012) |
| Tensilica HiFi Audio/ Voice DSP Licensed to Renesas Electronics (8/28/2012) |
| HDL Design House Appoints N.R.G. Technologies Its Representative for Israel (8/27/2012) |
| Arasan Chip Systems Announces Fast SD3.0-Compliant Hardware-Validation Platform (8/23/2012) |
| Digital Core Design's DoCD Provides On-Chip Debugger Via USB (8/23/2012) |
| Avery Design Systems Announces SCSI Express (SOP/PQI) Verification IP Solution (8/22/2012) |
| Intel Signs $20 Million Multi-Year License Agreement for Sonics System IP for SOC Platform Initiatives (8/22/2012) |
| intoPIX JPEG2000 Technology Integrated in Leonis Cinema's new CineMaster-Pro DCP Creator (8/22/2012) |
| Tehuti Networks Selects Kilopass Non-Volatile Memory IP for Its TN4010 Single-Port 10GbE Controller (8/22/2012) |
| The Portland Group Updates Its OpenCL Compiler for Multicore ARM (8/21/2012) |
| AuthenTec Unveils First Military-Grade Encryption Offering for Data Stored on Android Devices and Removable Storage Media (8/20/2012) |
| Codethink Announces Baserock Slab, a High-Performance Power-Efficient ARM Server (8/20/2012) |
| Evatronix Releases the First Semiconductor-Themed Android/iOS Game (8/20/2012) |
| intoPIX Unveils JPEG 2000 UHDTV 4K and 8K Codecs Integrated in Single 28-nm FPGA (8/20/2012) |
| Newest Holtek ARM Cortex-M3-Based 32-bit Flash MCU Series Boasts Large Memory and Rich Peripherals (8/20/2012) |
| SensorsCon 2013 Announces Call for Exhibitors, Sponsors and Speakers (8/20/2012) |
| Evatronix NAND Flash Controller Now Available with SafeFTL from HCC Embedded (8/16/2012) |
| TSMC Unveils Foundry's First 100-MHz Access Speed Embedded Flash IP (8/16/2012) |
| Cadence Publishes Comprehensive Book on Mixed-Signal Methodology (8/14/2012) |
| Creonic Announces DVB-RCS2 Turbo Decoder IP Core (8/14/2012) |
| Novatek in Volume Production with Three New Home-Entertainment SOCs Using Tensilica HiFi Audio DSP (8/14/2012) |
| ARM and GlobalFoundries Collaborate to Enable Next-Generation Devices on 20-nm and FinFET Process Technologies (8/13/2012) |
| Conexant Selects Tata Elxsi as Preferred Service Provider for its Digital Audio Processor (8/13/2012) |
| Novocell Semiconductor Announces Completion of Mil-Spec and Automotive Qualifications for Embedded Non-Volatile Memory (8/13/2012) |
| Xelic Announces 40G I.4/I.7 EFEC Core (8/13/2012) |
| Altera Deploys IC Manage to Improve Design Management and IP Reuse (8/9/2012) |
| ARM and Cadence Collaborate to Optimize ARM POP Solutions with Cadence Encounter Digital Platform (8/8/2012) |
| Synopsys Launches Technical Community Site Dedicated to Users of Verification IP (8/8/2012) |
| DMP SMAPH-S Products to Support OpenGL ES 3.0 API Standard (8/7/2012) |
| Vivante Shipping GPU Cores Designed to Support the Latest OpenGL ES 3.0 Specification (8/7/2012) |
| ARM Launches Second Generation of MALI-T600 Graphics Processors (8/6/2012) |
| STMicroelectronics Completes IP and Talent Acquisition from bTendo (8/6/2012) |
| Xylon Unveils 2D- and 3D-Graphics/HMI Reference Designs for Xilinx Zynq-7000 ZC702 Evaluation Board (8/2/2012) |
| ARM and Cavium Extend Relationship with ARMv8 Architecture License (8/1/2012) |
| Cavium Unveils Project Thunder to Target Next-Generation Cloud and Data Centers (8/1/2012) |
| DMP's PICA200 Lite 3D-Graphics IP Core adopted for Olympus Tough TG-1 Digital Camera (7/31/2012) |
| Digital Core Design Announces 10/100 Mb Media Access Controller with RMII (7/30/2012) |
| Tensilica Joins Wi-Fi Alliance to Provide Wireless Multi-Standard Modem Solutions (7/30/2012) |
| eMemory's Embedded MTP Solution Passes Verification in 65-nm Process Node (7/24/2012) |
| Latest Synopsys Virtualizer Release Speeds Virtual Prototype Creation by Up to 3X (7/24/2012) |
| ARM and TSMC Collaborate to Optimize Next-Generation 64-bit ARM Processors for FinFET Process Technology (7/23/2012) |
| QuickLogic's CSSPs Enable TI's Sitara AM335x Processor to Support High-Resolution Cameras (7/23/2012) |
| Arasan Chip Systems Announces Support of JEDEC eMMC 4.51 Standard (7/20/2012) |
| IDT Acquires NXP's Data Converter Assets and Alvand Technologies (7/19/2012) |
| Rockchip Licenses Arteris FlexNoC Interconnect IP for Android-Based Tablets (7/19/2012) |
| CAST Opens IP Cores Sales Office in China (7/18/2012) |
| TVS Validates UVM-Based VIP with Aldec's Riviera-PRO (7/17/2012) |
| Samsung Selects AuthenTec's VPN Security for New Android Smartphones and Tablets (7/16/2012) |
| Systemcom Launches New Analog Front-End IP with 13-bit ADC at TSMC 180nm (7/16/2012) |
| Xylon Now Shipping Upgraded logiCAN CAN2.0B Bus Controller IP Core (7/16/2012) |
| Carbon Design Systems Partners with Imagination Technologies for Virtual Models (7/13/2012) |
| Dolphin Integration's Standard Cell Library Enhanced with Pulsed Latches (7/13/2012) |
| EDA Consortium Reports Revenue Increase for Q1 2012 (7/13/2012) |
| ACE's CoSy Compiler Framework Outperforms LLVM for the ARM9 Processor (7/12/2012) |
| Cadence Adds New Capabilities to Its PCI Express Verification IP Including PIPE4 Support (7/11/2012) |
| Altera Reduces Design Complexity in High-Performance 40GbE/100GbE Designs with Latest IP Core Offering (7/10/2012) |
| Cosmic Circuits Announces Silicon Availability of MIPI M-PHY in 28nm (7/10/2012) |
| Synopsys and SMIC Announce DesignWare IP for 40-nm Low-Leakage Process (7/10/2012) |
| China's Vango Technologies Licenses MIPS Technologies Processor IP for Smart-Grid Solutions (7/9/2012) |
| Mentor Graphics Announces Support for the Multi-Threaded MIPS32 34K Core with the Nucleus SMP RTOS (7/9/2012) |
| New MIPS-Based Android 4.0 Tablet Coming Soon to India, Latin America and Europe (7/9/2012) |
| Novocell Semiconductor Expands OTP NVM IP Product Line (7/9/2012) |
| Open-Silicon's Interlaken IP Core Selected for Netronome's Next-Generation Flow Processors (7/9/2012) |
| Synopsys DesignWare IP for PCI Express with Support for Low-Power Sub-States Successfully Taped Out in Multiple Designs (7/9/2012) |
| Xylon Announces logiI2C Master Controller IP Core for Xilinx FPGAs (7/9/2012) |
| Cadence Digital PHY Design IP Adopted by Brite Semiconductor (7/3/2012) |
| ChipStart and Digital Core Combine Strengths (7/3/2012) |
| Fabless Sector Outperforms the Overall Industry in the First Quarter, Says GSA (7/3/2012) |
| MIPS Technologies and Broadcom Sign Broad Patent and Technology License Agreement (7/3/2012) |
| Takumi Graphics IP Cores Reference Designs Available on S2C Prototyping Platform (7/3/2012) |
| Atmel Delivers Highest-Density Embedded Flash Cortex-M4 Processor-Based MCU (7/2/2012) |
| CAST Signs Picosem Technologies as IP Cores Partner in India (7/2/2012) |
| Real Time Logic Extends Machine-to-Machine Device Security and Encryption to NXP's ARM Cortex-M MCUs (7/2/2012) |
| SRS Labs Completes Integration of TruMedia onto Hexagon DSP based Snapdragon Platforms (7/2/2012) |
| Digital Core Design Introduces New Version of the Motorola 68000 16/32-bit MCU with Linux, MAC and Debugger (6/28/2012) |
| Elliptic Technologies Joins ARM TrustZone Ready Program (6/28/2012) |
| Integre Technologies Announces HyperLink DSP Interface FPGA Core (6/27/2012) |
| Xilinx Integrated Block for the PCI Express Gen3 Standard Accelerates Productivity and Increases System Performance (6/27/2012) |
| CEVA and eyeSight Announce Availability of Software-Based Gesture Recognition Solution for the CEVA-MM3101 Imaging and Vision Platform (6/26/2012) |
| Global Unichip Announces 10GBase-KR, Multi-Standard SerDes IP (6/26/2012) |
| Javelin Semiconductor Chooses Kilopass NVM IP Core for MIPI RFFE Digital Interface in Next-Generation CMOS Power Amplifiers (6/26/2012) |
| STMicroelectronics Delivers New 32-Bit ARM Cortex Microcontrollers for Projects Needing Digital Signal Control at Competitive Cost (6/26/2012) |
| Discretix Content Protection Solutions Incorporated in Qualcomm's Snapdragon StudioAccess Technology (6/25/2012) |
| RedCat Devices' Radiation-Hardened SRAM Fabricated in TowerJazz's 0.18-µm Process Flow Withstands 15-Mrad Total Ionization Dose (6/25/2012) |
| Freescale Names IAR Embedded Workbench Toolchain of Choice for ZigBee Development (6/20/2012) |
| Market Research Forecasts Semiconductor IP Market Growth at 18% CAGR Through 2015 (6/20/2012) |
| Recore Systems Launches OptiumIP.com with Turnkey DSP Accelerator IP Cores (6/20/2012) |
| SENSIO 3D Decoder Integrated in Christie SKA-3D Processor (6/20/2012) |
| SMIC and AlgolTek Announce Availability of digniPHY for USB 3.0 on SMIC's 0.13-µm Technology (6/20/2012) |
| SMIC and Brite Semiconductor's 40LL Dual-Core ARM Cortex-A9 Test-Chip Achieves 1.3GHz (6/20/2012) |
| Tiempo Announces Silicon Validation of TESIC Secured Platform (6/20/2012) |
| Timesys Joins ARM/Avnet Embedded Software Store (6/20/2012) |
| MIPI Alliance and USB 3.0 Promoter Group Announce Availability of SuperSpeed USB Inter-Chip Specification (6/19/2012) |
| ChipStart and Digital Core Design Partner on Sales and Marketing (6/18/2012) |
| New ARM Mali-450 MP Graphics Processor Provides Next-generation Graphics Performance for Smart-TV and Smartphone Applications (6/18/2012) |
| Noesis Technologies Achieves Xilinx Alliance Membership (6/18/2012) |
| Toshiba Selects SonicsSX for Next-Generation Product Development (6/18/2012) |
| Xilinx Targets Reduced OpEx and CapEx for Network Operators with Expanded FEC IP Core Offering (6/18/2012) |
| Imagination Adds to PowerVR Series6 Rogue Family (6/15/2012) |
| Imagination Announces New Generation PowerVR D4500MP Video Decoder and E4500MP Video Encoder (6/15/2012) |
| Imagination Meta Processor Delivers Dolby MS11 Multistream for Premium Audio (6/15/2012) |
| Imagination Optimizes its IP Capabilities with TSMC on Latest Silicon Process Technologies (6/15/2012) |
| Nationz Technologies Licenses MIPS Technologies Processor Cores for Mobile Payment Solutions (6/14/2012) |
| Dolphin Integration Announces Break-Through in Logic Design Improving Performance (6/13/2012) |
| Altera Quartus II Software Delivers up to 4X Faster Compile Times; Expands Support for 28-nm FPGAs (6/12/2012) |
| AMD, ARM, Imagination, MediaTek and TI Form the HSA Foundation to Promote Heterogeneous Computing (6/12/2012) |
| CEVA Announces Availability of TD-SCDMA Software IP for CEVA-XC DSP Family (6/12/2012) |
| Renesas Electronics and Renesas Mobile License ARM Processor IP for Next-Generation Communications Processors and Application Processors (6/12/2012) |
| Nominations for EDA Industry's Annual Phil Kaufman Award Open Through June 30 (6/11/2012) |
| IAR Systems Enhances Its Development Tools for ARM (6/7/2012) |
| Sonics and Arasan Collaborate on End-to-End IP Subsystems for Mobile Market (6/5/2012) |
| Accellera Systems Initiative Rolls Out the Unified Coverage Interoperability Standard (6/4/2012) |
| CEVA and VWorks Announce Availability of Virtual Prototyping Platforms Featuring CEVA DSPs (6/4/2012) |
| Chip Path Announces SOC Architectural Assembly and Floorplanning System (6/4/2012) |
| Intrinsic-ID Launches Quiddikey-FLEX Flexible Key-Management IP Core (6/4/2012) |
| IPL Alliance Announces IPL 2.0 and Appoints New Chair for Constraint Working Group (6/4/2012) |
| Northwest Logic Uses Blue Pearl Software's Analyze to Maximize IP Core Quality (6/4/2012) |
| S2C Releases New Prototype-Ready ARM11 and ARM9 Modules for FPGA-Based Prototypes (6/4/2012) |
| Analog Bits Unveils Integrated Sensor Macro Family (5/31/2012) |
| Cortus Launches APS5 32 bit Microcontroller IP Core for High-Performance Embedded ASIC Designs (5/31/2012) |
| Design and IP Quality-Management Solutions (5/31/2012) |
| 8051 Microcontroller IP Cores from CAST Even More Efficient with New Single-Wire Debug (5/30/2012) |
| Dennis Brophy to Receive Accellera Systems Initiative Leadership Award (5/30/2012) |
| Evatronix to Showcase its Latest Multimedia IP at DAC (5/30/2012) |
| Avery Design Systems Adds NVM Express to Storage Standards Verification IP Solutions (5/29/2012) |
| Cadence Announces Updated Design and Verification IP for DDR PHY Interface (5/29/2012) |
| DFI Technical Group Releases Version 3.1 of Its High-Speed Memory Controller and PHY Interface Specification (5/29/2012) |
| MagnaChip and YMC Enter into a Joint Development Agreement for MTP-IP Devices (5/29/2012) |
| OCP-IP Publishes New "Intro to OCP" Book (5/29/2012) |
| Toshiba ARM Cortex-M0 Microcontroller Optimized for Smart Meters (5/29/2012) |
| Vivante Is First GPU IP Supplier to Pass OpenCL 1.1 Conformance Test (5/29/2012) |
| GainSpan Licenses Cosmic Circuits IP (5/28/2012) |
| Carbon Design Systems and Cadence Partner for IP Optimization (5/24/2012) |
| MOSIS to Offer Cortus APS3R Microcontroller Core to SOC Designers (5/24/2012) |
| Uniquify Launches ideas2silicon Design Services Platform (5/24/2012) |
| OCP-IP Releases OCP 3.1 Specification into Member Review (5/23/2012) |
| Silicon Image Introduces Low-Power Dual-Mode Transmitter IP Core Supporting Both HDMI and MHL Connectivity Standards (5/23/2012) |
|
Magazine & Journal articles on Selecting and Integrating IP |
| Maximizing the Value of Your Internal IP SOCcentral (5/15/2013) |
| Customizing SRAM Content to Obtain Truly Differentiated Products Chip Estimate Corp. (5/14/2013) |
| How Small Vendors Compete on Analog IC Market EE Times Test & Measurement Designline (4/29/2013) |
| The Use of FinFETs in IP Design Chip Estimate Corp. (4/23/2013) |
| Using Audio Codec IP as the Digital Audio Hub in Mobile Multimedia Systems EDN Magazine (4/23/2013) |
| FPGAs Offer Cost-Effective, Flexible Solutions for Remote Radio Heads EE Times Programmable Logic Designline (4/18/2013) |
| Complex Standards Demand New Approaches to IP Quality Chip Estimate Corp. (4/16/2013) |
| Stitch and Ship No Longer Viable EE Times EDA Designline (4/15/2013) |
| SOC FPGAs Combine Performance and Flexibility EDN Magazine (4/10/2013) |
| SSM Policy-Driven System Management Updates SOC Architecture to Meet Today's Operation Complexities Chip Estimate Corp. (4/9/2013) |
| Yes, Virginia, There Is a Stitch-and-Ship SOCcentral (4/5/2013) |
| Building Your UVM Verification Environment for Cache-Coherent Interconnects Design & Reuse (4/4/2013) |
| Extreme Code Density: Energy Savings and Methods Chip Estimate Corp. (4/2/2013) |
| Dynamic Partitioning Speeds Memory Characterization EE Times Memory Designline (3/25/2013) |
| The Challenges of Using Open-Market IP in ASIC Designs Chip Estimate Corp. (3/19/2013) |
| Hardware (and Software) Implications of Endianness in SOC Design Embedded.com (3/17/2013) |
| Formal Verification Works Well for Connectivity Checking SOCcentral (3/15/2013) |
| Tensilica Acquisition to Accelerate Cadence Core Strategy Electronic Engineering Times (EE Times) (3/13/2013) |
| The Coming Impact of Mobile PCI Express (M-PCIe) on SOCs and Devices Chip Estimate Corp. (3/12/2013) |
| Virtual Prototyping Methodology to Boot Linux on the ARM Cortex A15 EE Times EDA Designline (3/11/2013) |
| Virtual Prototyping Methodology to Boot Linux on the ARM Cortex A15 EE Times EDA Designline (3/11/2013) |
| Analyzing the Options in High-Bandwidth System Interconnect Altera Corp. (3/8/2013) |
| State of RTL-based Design: Is It Time to Move Beyond? Design & Reuse (2/25/2013) |
| Using 3rd-Party IP in ASIC/SOC Design EE Times EDA Designline (2/25/2013) |
| Voltage-Controlled MRAM: Status, Challenges and Prospects EE Times Memory Designline (2/25/2013) |
| Designing Low-Power Video Image Stabilization IP for FPGAs EE Times Militray & Aerospace Highlights (2/19/2013) |
| A Call to Action: How 20nm Will Change IC Design SOCcentral (2/8/2013) |
| Demystifying Analog and Mixed-Signal ASICs SOCcentral (2/8/2013) |
| Accelerated VIP Solves Firmware and Driver Integration and Validation Trade-Offs Tech Design Forum (1/31/2013) |
| Extreme Code Density: Energy Savings and Methods Chip Estimate Corp. (1/29/2013) |
| Verification IP: The Questions You Should Ask Tech Design Forum (1/24/2013) |
| Understanding SATA FIS-Based Switching Chip Estimate Corp. (1/22/2013) |
| Get More out of System Architectures Tech Design Forum (1/18/2013) |
| Smart Power Hook-Up Methodology for Memories on SOCs EDN Magazine (1/16/2013) |
| Why USB 3.0 Will Drive SOC Verification in 2013 Chip Estimate Corp. (1/15/2013) |
| Integrating Large-Capacity Memory in Advanced-Node SOCs EE Times Memory Designline (1/14/2013) |
| The SOC Interconnect-Verification Challenge SOCcentral (1/14/2013) |
| RTL Analysis for Complex FPGA Designs Using a Grey Cell Methodology SOCcentral (1/2/2013) |
| Customizing SRAM Content to Obtain Truly Differentiated Products Chip Estimate Corp. (12/25/2012) |
| Seismic Shifts Await EDA in a More-than-Moore World Electronic Design Magazine (12/20/2012) |
| Smashing Through the Mobile Device Memory Bottleneck Chip Estimate Corp. (12/11/2012) |
| High-Performance Logic Libraries for Core Hardening Chip Estimate Corp. (12/4/2012) |
| Debunking Myths About Analog IP at 20nm EE Times Planet Analog (12/3/2012) |
| Design Reuse without Verification Reuse Is Useless EE Times EDA Designline (11/26/2012) |
| Alternative NVM Technologies Require New Test Approaches-Part 2 EE Times Memory Designline (11/20/2012) |
| Selecting Embedded SRAM to Meet LowiVoltage Requirements Chip Estimate Corp. (11/20/2012) |
| Alternative NVM Technologies Require New Test Approaches-Part 1 EE Times Memory Designline (11/13/2012) |
| ARM vs. Incumbent Microprocessor Architectures EDN Magazine, (11/13/2012) |
| Optimizing Memory Design EE Times Memory Designline (11/13/2012) |
| What's the Difference Between de Jure and de Facto Standards? Electronic Design Magazine (11/13/2012) |
| Protecting Display Data in TrustZone-Enabled SoCs with the Evatronix Panta Family of Display Processors Design & Reuse (11/8/2012) |
| ARM-Based Android Hardware/Software Design Using Virtual Prototypes-Part 2: Building a Sensor Subsystem EE Times Embedded (11/7/2012) |
| Implementing Digital Processing for Automotive Radar Using SOC FPGAs EE Times Programmable Logic Designline (11/6/2012) |
| SSM Policy Driven System Management Updates SoC Architecture to Meet today's Operation Complexities Chip Estimate Corp. (11/6/2012) |
| Right-Sizing Your Processor Selection EDN Magazine (11/5/2012) |
| ARM-Based Android Hardware/Software Design Using Virtual Prototypes-Part 1: Why Virtualize? EE Times Embedded (10/27/2012) |
| RTL Analysis for Complex FPGA Designs Using a Grey Cell Methodology EE Times Programmable Logic Designline (10/26/2012) |
| Vendor-Independent RTL Memory BIST Insertion and Verification SOCcentral (10/23/2012) |
| Understanding 28-nm SOC Design with ARM-Based Cores Electronic Design Magazine (10/19/2012) |
| One Processor to Rule Them All? EDN Magazine (10/18/2012) |
| Processor Architectures: the Sweet-Spot Spectrum EDN Magazine (10/18/2012) |
| Marketing and Technology Collide in Competitive Chip Design Electronic Design Magazine (10/11/2012) |
| The IP Blame Game SOCcentral (10/10/2012) |
| M-PHY Benefits and Challenges Chip Estimate Corp. (10/9/2012) |
| Multicore ARM SOCs Face Cache Coherency Dilemma Chip Estimate Corp. (10/2/2012) |
| Addressing Memory Performance for 100G Ethernet Networking Chip Estimate Corp. (9/18/2012) |
| Designing a NVMe-Compliant PCIe SSD Chip Estimate Corp. (9/4/2012) |
| 6 Reasons You Should Customize Your DSP Cores Chip Estimate Corp. (9/1/2012) |
| Growing Audio Requirements in SOCs EE Times Audio Designline (8/23/2012) |
| Solutions for Mixed-Signal SOC Verification SOCcentral (8/21/2012) |
| Proposal for a Dynamically Reconfigurable Processor Architecture with Multi-Accelerator Design & Reuse (8/20/2012) |
| Leapfrogging the Competition Through Smart IP Selection SOCcentral (8/17/2012) |
| Move to Broader Coverage in SOC Verification Metrics Electronic Design Magazine (8/16/2012) |
| Growing Audio Requirements in SOCs EDN Magazine (8/7/2012) |
| How Flash and DRAM Growth Trends are Reshaping the Memory Industry Chip Estimate Corp. (8/7/2012) |
| Breaking Through the Embedded Memory Bottleneck-Part 1 EE Times Memory Designline (7/30/2012) |
| ASIC Implementation of a Speech Detector IP-Core for Real-Time Speaker Verification Design & Reuse (7/24/2012) |
| Integrate More Analog into Your Digital Designs Electronic Design Magazine (7/24/2012) |
| 8051s in the Spectrum of Microcontroller Choices SOCcentral (7/20/2012) |
| Using Code-Coverage Analysis to Verify 2D Graphic Engines in Automotive Apps EE Times Automotive Designline (7/20/2012) |
| Design of a 8051 Microcontroller in FPGA with Reconfigurable Instruction Set Design & Reuse (7/19/2012) |
| The Fundamentals of Integrating USB 3.0 IP on an SoC Electronic Design Magazine (7/18/2012) |
| Understanding FPGA Processor Interconnects Electronic Design Magazine (7/17/2012) |
| Embedded Success: It's About More than Just the Core Electronic Design Magazine (7/11/2012) |
| Integrating IDE and RTOS for ARM-based Development EE Times Industrial Control Designline (7/11/2012) |
| Enabling Error Resilience Throughout the Embedded System EE Times Programmable Logic Designline (7/10/2012) |
| Understanding Virtual Sensors: From Sensor Fusion to Context-Aware Applications Electronic Design Magazine (7/10/2012) |
| Anti-Fuse Memory Provides Robust, Secure NVM Option EE Times Memory Designline (7/5/2012) |
| How-to Guide for On-Chip Memory Electronics Weekly (6/26/2012) |
| The IP Distribution Challenge SOCcentral (6/15/2012) |
| Pseudo-Hardening in SOC Design EDN Magazine (5/25/2012) |
| Latest FPGAs Show Big Gains in Floating-Point Performance SOCcentral (5/16/2012) |
| An Accurate DRAM Model SOCcentral (5/14/2012) |
| How to Use the CORDIC Algorithm in Your FPGA Design EE Times Programmable Logic Designline (5/12/2012) |
| Augmenting the Transaction Generator with New DRAM and Workload Models SOCcentral (5/11/2012) |
| Lessons in Developing and Deploying OVM-Compliant VIP Design & Reuse (5/3/2012) |
| Reaching for the Cloud: What's Next for Interconnects SOCcentral (4/27/2012) |
| ADC Performance: What's Jitter Got to Do with It? Electronic Design Magazine (4/25/2012) |
| Resistive RAM: The Future Embedded Non-Volatile Memory? SOCcentral (4/9/2012) |
| Optimizing Performance, Power, and Area in SOC Designs Using MIPS Multi-Threaded Processors EE Times EDA Designline (4/4/2012) |
| Unified C-Programmable ASIP Architecture for Multi-Standard Viterbi, Turbo and LDPC Decoding Design & Reuse (3/28/2012) |
| Ensuring Successful Third-Party Intellectual Property Integration EE Times EDA Designline (3/26/2012) |
| Fundamentals of Floor Planning a Complex SOC Electronic Design Magazine (3/21/2012) |
| Integrating Audio Codecs in Next-Generation SOCs for Smartphones and Tablets EE Times Audio Designline (3/20/2012) |
| Software-Generated BCH As a Way to Solve Challenges of Providing Multiple Configuration IP Design & Reuse (3/6/2012) |
| Mixed-Signal IP Design Challenges in 28nm and Beyond Design & Reuse (3/1/2012) |
| Formal Techniques for Protocol Verification: A Case Study on Verifying the ARM ACE Protocol Electronic Design Magazine (1/11/2012) |
| How Formal MDV Can Eliminate IP Integration Uncertainty EE Times EDA Designline (1/9/2012) |
| Functional Coverage Analysis for IP Cores and an Approach to Scale Down Overall Simulation Time Design & Reuse (1/3/2012) |
| Automating Design Rule Waivers in SOC IP Reuse Electronic Design Magazine (12/27/2011) |
| Prototyping Mesh-of-Tree NOC-Based MPSOC on Mesh-of-Tree FPGA Devices Design & Reuse (11/23/2011) |
| Overcoming 40G/100G SerDes Design And Implementation Challenges EE Times EDA Designline (11/2/2011) |
| Open Standards Are Better than Open Source Electronics Weekly (10/26/2011) |
| The Basics of Low-Power Programming on the Cortex-M0 EE Times Embedded (10/25/2011) |
| Big.LITTLE Processing with ARM Cortex-A15 and Cortex-A7 EE Times MCU Designline (10/24/2011) |
| Implementing High-Speed USB Functionality with FPGA- and ASIC-Based Designs EE Times Programmable Logic Designline (10/18/2011) |
| Basics of Porting C-code to and between ARM CPUs: ARM7TDMI and Cortex-M0 EE Times Embedded (10/17/2011) |
| Breaking the Memory-Performance Bottleneck SOCcentral (10/17/2011) |
| Argument for Anti-Fuse Non-Volatile Memory in 28-nm High-K Metal Gate EE Times Memory Designline (10/15/2011) |
| 25-28Gbps SerDes Design and Implementation Challenges Chip Estimate Corp. (10/4/2011) |
| A Practical Approach to IP Quality Inspection EE Times EDA Designline (9/26/2011) |
| Managing IP Quality in the SOC Era Requires a Purpose-Built DM Approach Electronic Engineering Times (EE Times) (9/19/2011) |
| Breaking the Language Barriers: Using Coverage Driven Verification to Improve the Quality of IP Design & Reuse (9/1/2011) |
| Many-Core: Finding the Best Multi-Processing Tile EE Times EDA Designline (8/29/2011) |
| Cryptography in Software or Hardware: It Depends on the Need EE Times Embedded (8/28/2011) |
| Basics of Core-Based FPGA Design-Part 4: Implementing a Design EE Times Embedded (8/22/2011) |
| Basics of Core-Based FPGA Design-Part 2: System Design Considerations EE Times Embedded (8/21/2011) |
| Basics of Core-Based FPGA Design-Part 3: Picking the Right Core Options EE Times Embedded (8/21/2011) |
| Basics of Core-Based FPGA Design-Part 1: Core Types & Trade-Offs EE Times Embedded (8/17/2011) |
| Interconnect Solutions for 40G/100G Systems Design & Reuse (8/4/2011) |
| Designing with Core-Based High-density FPGAs EE Times Embedded (7/27/2011) |
| SPVR: An IP Core for Real-Time Speaker Verification Design & Reuse (7/21/2011) |
| Tracking PLL Design Through the Decades-Part 1 EDN Magazine (7/14/2011) |
| Tracking PLL Design Through the Decades-Part 2 EDN Magazine (7/14/2011) |
| Creating an SOC Virtual Platform for Embedded Software Development Electronic Design Magazine (6/28/2011) |
| Application Driven Network on Chip Architecture Exploration & Refinement for a Complex SOC Design & Reuse (6/20/2011) |
| Breaking the Language Barriers: Using Coverage Driven Verification to Improve the Quality of IP Design & Reuse (6/20/2011) |
| Moore's Law; the Bifurcation of the Semiconductor Industry and 3-D integration Electronic Engineering Times (EE Times) (6/16/2011) |
| A Case for Custom Power Management ASICs Design & Reuse (6/8/2011) |
| Adopting a Flexible FPGA Verification Methodology SOCcentral (6/1/2011) |
| Power Optimization in Image Superscalar IP Design & Reuse (5/26/2011) |
| Improving Today's Multimedia Products with 3rd-Party Audio IP Solutions EE Times Audio Designline (5/25/2011) |
| Advanced Power Management in Embedded Memory Subsystems Design & Reuse (5/19/2011) |
| Using Cost-Effective and Secure Field-Programmable 1T-OTP to Emulate MTP SOCcentral (4/28/2011) |
| Plan Strategies for Adopting Model-Based Design for Embedded Applications: Part 4 - Implementation, Verification and Validation EE Times Automotive Designline (4/21/2011) |
| Systematic Approach to Verification of a Mixed-Signal IP: HSIC PHY Case Study Design & Reuse (4/21/2011) |
| Minimal Effort Chip Design Using IP Design & Reuse (4/14/2011) |
| ARM vs. Intel: A Successful Stratagem for RISC or Grist for CISC's Tricks? EDN Magazine (4/7/2011) |
| Get the Lowdown on Accellera's VIP and UVM Chip Design Magazine (4/1/2011) |
| In IP We Trust? Chip Design Magazine (4/1/2011) |
| IP Gets Smarter SOCcentral (4/1/2011) |
| Automating Design Rule Waivers in SOC IP Reuse Design & Reuse (3/31/2011) |
| Complete NAND Flash Solution: Logic, PHY and File System Software Design & Reuse (3/31/2011) |
| Factors Compelling Greater Use of Embedded One-Time Programmable Memory SOCcentral (3/24/2011) |
| Vertically Integrated MIPI Solutions Design & Reuse (3/24/2011) |
| Analog IP for Multimedia SOCs: An Eye on a World of Essential Analog Features EE Times Planet Analog (3/22/2011) |
| Verification of USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment Design & Reuse (3/17/2011) |
| Hardware Co-Verification Using VMM HAL-SCEMI Design & Reuse (3/10/2011) |
| Planning Reset Strategy: Flow and Functionality in OVC EE Times EDA Designline (3/9/2011) |
| CPUs in FPGAs: Many Faces to a Trend EDN Magazine (3/3/2011) |
| Adding Encryption to Disk Drives Is Made Easy Using an IP Core EE Times Programmable Logic Designline (3/2/2011) |
| Virtual Channels Hardware Support in Switches in Relation to NoC Costs, Functions and Features Design & Reuse (2/21/2011) |
| Hardware Solutions to the Challenges of Multimedia IP Functional Verification Design & Reuse (2/16/2011) |
| Importance of Dynamic Programming for Achieving Hard Breakdown in Anti-Fuse Technology Design & Reuse (2/3/2011) |
| How Are Competitors Differentiating Cortex-M3 based MCUs? New Electronics Magazine (1/10/2011) |
| Choosing an Effective Embedded SOC ASIC Design Strategy EE Times Embedded (12/13/2010) |
| A Memory Subsystem Model for Evaluating Network-on-Chip Performance Design & Reuse (12/2/2010) |
| A Methodology for Describing Analog/ Mixed-Signal Blocks as IP Design & Reuse (11/25/2010) |
| The Expanding Floating-Point Performance Gap Between FPGAs and Microprocessors HPCwire (11/22/2010) |
| Innovation Led Business Models for IP's In Product Engineering Design & Reuse (11/18/2010) |
| Trace-Based Approach for Unit-Level Debug and Verification of C/C++ IP Models Design & Reuse (11/18/2010) |
| New IC Verification Techniques for Analog Content EE Times EDA Designline (11/17/2010) |
| SOC DFT Verification With Static Analysis and Formal Methods Test & Measurement World (11/17/2010) |
| eFPGA Creator GUI Tools Suite: A Complete Hardware and Software Infrastructure for Creating Customizable eFPGA IP Blocks Design & Reuse (11/4/2010) |
| Will IP Use Increase In Forthcoming SOC Design? Electronic Engineering Times (EE Times) (11/4/2010) |
| A Developer's Insight Into ARM Cortex-M Debugging EE Times Embedded (11/3/2010) |
| Application Specific IP: Ensuring Semiconductor IP Quality Design & Reuse (10/28/2010) |
| DSP Options to Accelerate Your DSP+FPGA Design EE Times Signal Processing DesignLine (10/25/2010) |
| HW/SW Interface Generation Flow Based on Abstract Models of System Applications and Hardware Architectures Design & Reuse (10/25/2010) |
| Use of an IP-core Development Process to Achieve Time-to-Market and Quality Assurance In a Multi-Project Environment Design & Reuse (10/25/2010) |
| Design Environment for the Support of Configurable Network Interfaces in NoC-based Platforms Design & Reuse (10/21/2010) |
| EDA's Next Step: System-Level Design Automation Electronic Design Magazine (10/20/2010) |
| How to Choose Great IP Design & Reuse (10/6/2010) |
| A Primer for Successful Integration of Complex Hard IP In Physical Design EDN Magazine (9/13/2010) |
| IP Integration: Is It the Real System-Level Design? EDN Magazine (8/16/2010) |
| Reduce Embedded SOC Design Cost and Optimize IP Integration EE Times Embedded (8/16/2010) |
| Selecting an AES Solution SOCcentral (8/2/2010) |
| Customized FPGA board for ASIC Prototyping: A Novel Approach with Pre-designed Blocks and Modular FPGA Design & Reuse (7/29/2010) |
| IP Re-Engineering and Design Methodology Design & Reuse (7/29/2010) |
| Defining a Universal Verification Methodology SOCcentral (7/23/2010) |
| Verifying Your Configurable OCP Interfaces EE Times Embedded (6/29/2010) |
| Is IP Integration the Real High-Level Design? EDN Magazine (6/21/2010) |
| Advancing Network Packet Management and Security Using Silicon Based Subsystem IP Solutions Design & Reuse (6/17/2010) |
| Altering the SOC Design Flow EDN Magazine (6/17/2010) |
| Creating Virtual Platforms Using the OCP-IP Modeling Kit Design & Reuse (6/17/2010) |
| Power Optimization In Image Superscalar IP Design & Reuse (6/17/2010) |
| Power-Grid Analysis on SOC Graphics Chip Design EDN Magazine (6/17/2010) |
| Repeatable Results with Design Preservation EE Times Programmable Logic Designline (6/17/2010) |
| The Transformation of Silicon to System Design Electronic Products Magazine (6/1/2010) |
| Code Coverage Convergence In Configurable IP Design & Reuse (5/27/2010) |
| Power Management for Optimal Power Design EDN Magazine (5/27/2010) |
| Selecting the Right Nonvolatile Memory IP: Applications and Alternatives EE Times Embedded (5/24/2010) |
| The "Off-the-Shelf" IPs for Today's SoCs EE Times Embedded (5/24/2010) |
| Implementing PCI Express Bridging Solutions In an FPGA Embedded Computing Design (5/19/2010) |
| Producing and Verifying Quality FPGA IP Embedded Computing Design (5/19/2010) |
| Protecting FPGAs from Power Analysis Attacks EE Times Programmable Logic Designline (5/18/2010) |
| Building Cost-Effective and Robust SOC-based Network Appliances EE Times Embedded (5/17/2010) |
| A Novel Mesh Architecture for On-Chip Networks Design & Reuse (5/16/2010) |
| Design Reuse – It’s Time for New IP-Creation Tools SOCcentral (5/10/2010) |
| Implementing Different Power Features In an IP Design & Reuse (4/29/2010) |
| Integrating Analog Video Interface IP Into SoCs Delivers Superb Image Quality: Part 2 EE Times EDA Designline (4/29/2010) |
| An Analysis of Blocking versus Non-Blocking Flow Control In On-Chip Networks Design & Reuse (4/22/2010) |
| Choosing the Best Standard Cell Library without Falling Into the Traps of Traditional Benchmarking Methods Design & Reuse (4/22/2010) |
| Scratching the Surface: The 2010 EDN DSP Directory EDN Magazine (4/22/2010) |
| An Application-Specific Processor for Many-Core Architectures Design & Reuse (4/15/2010) |
| Incorporating Quality Into Reusable Interface IP Design & Reuse (4/15/2010) |
| Integrating Analog Video Interface IP Into SOCs Delivers Superb Image Quality: Part 1 EE Times EDA Designline (4/7/2010) |
| A Step-By-Step Methodical Approach for Efficient Mixed-Language IP Integration Design & Reuse (3/22/2010) |
| Building Quality Assurance Into Your Hardware: EDA Is Not Enough! EE Times EDA Designline (3/17/2010) |
| Selecting an Embedded MCU: How to Avoid the Evaluation Trap? Design & Reuse (3/11/2010) |
| Embedded Symmetric MultiProcessing System On a SoC with 1.6GHz PowerPC IP in 45nm Design & Reuse (3/4/2010) |
| Evolving to a Total IP Solutions to Accelerate SOC Design Design & Reuse (3/4/2010) |
| Incorporating Quality Into Reusable IP EE Times Embedded (2/26/2010) |
| Hardware Solutions to the Challenges of Multimedia IP Functional Verification Design & Reuse (2/25/2010) |
| Software Architecture for IP verification in Operating System Environment Design & Reuse (2/25/2010) |
| Reusable VHDL IP In the Real World Design & Reuse (2/18/2010) |
| Guidelines for Complex SOC Verification EE Times EDA Designline (2/15/2010) |
| Re-Configurable Platform for Design, Verification and Implementation of SOCs Design & Reuse (2/11/2010) |
| Tools Accurately Simulate Noise in Mixed-Signal ASICs EDN Magazine (2/4/2010) |
| Improving Software Development and Verification Productivity Using IP-Based System Prototyping Design & Reuse (2/1/2010) |
| Increasing Bandwidth In Industrial Applications with FPGA Co-Processors EE Times Programmable Logic Designline (2/1/2010) |
| A Recipe for Verification IP: The Role of Methodology Design & Reuse (1/26/2010) |
| A Nuts and Bolts Engineering Approach to Using Open Source IP EE Times Embedded (1/25/2010) |
| Designing Serial ATA IP Into Your Embedded Storage Device Design EE Times Embedded (12/14/2009) |
| The Evolving Landscape of Digital Signal Processing EDN Magazine (12/3/2009) |
| The Best of Both Worlds: Optimizing OCP Slave Memory Behavior EE Times EDA Designline (11/19/2009) |
| Graphics Processing: When DIY Just Doesn't Make Sense EE Times EDA Designline (11/15/2009) |
| What If the IP You Are Looking for Does Not Exist? Design & Reuse (10/29/2009) |
| A Set of VHDL IPs to Evaluate Performance of Netwoks-on-Chip Design & Reuse (10/22/2009) |
| A Processor and DSP IP Selection Checklist SOCcentral (10/15/2009) |
| Implementing an All-Digital PHY and Delay-Locked Loop for High-Speed DDR2/3 Memory Interfaces EDN Magazine (10/15/2009) |
| Use of an IP core Development Process to Achieve Time-to-Market and Quality Assurance in a Multi-Project Environment Design & Reuse (10/15/2009) |
| Outsourcing SoC Network Design Just Makes Sense Electronic Design Magazine (10/11/2009) |
| IP Quality Lies Beyond Compliance Testing EDN Magazine (10/8/2009) |
| Using Tcl to Create a Virtual Component in Verilog EE Times Embedded (10/2/2009) |
| DFM-Compliant IP: Why You Need It, How You Get It SOCcentral (9/9/2009) |
| How FPGAs Can Address MCUs' General-Purpose I/O Scaling Wall EE Times Programmable Logic Designline (9/9/2009) |
| Protocol Abstraction Views Simplify Chip Interconnect Debugging SOCcentral (9/7/2009) |
| The Key to Seamless and Rapid IP Integration SOCcentral (9/1/2009) |
| Improving Software Driver Development and Hardware Verification Productivity using Virtual Platforms Design & Reuse (8/27/2009) |
| Placement of Different Type Nodes In a Network-on-Chip Graph Design & Reuse (8/13/2009) |
| First-Pass Success In Silicon Packaging EDN Magazine (8/6/2009) |
| Techniques for Implementing High-Performance Processor Cores EDN Magazine (8/6/2009) |
| Changing SoC Design Methodologies to Automate IP Integration and Reuse EE Times EDA Designline (7/27/2009) |
| Virtual Multi-Cores Simplify Real-Time System Design EE Times Embedded (7/27/2009) |
| Versatile OTP Can Replace Several Memories Chip Estimate Corp. (7/15/2009) |
| Debugging Hybrid FPGA Logic/Processor Designs Electronic Products Magazine (7/1/2009) |
| Should Dual-Rail Go Mainstream in Deep Nanometer Era? Electronic Design Magazine (6/29/2009) |
| Little-Known Flash-Memory Features Protect Data and IP EDN Magazine (6/25/2009) |
| SuperSpeed USB 3.0: Ubiquitous Interconnect for Next Generation Consumer Applications Design & Reuse (6/22/2009) |
| Generic and Automatic Specman-based Verification Environment for Image Signal Processing IPs Design & Reuse (6/18/2009) |
| SpiritEd: A Register Specification System integrating IP-XACT and Adobe FrameMaker Design & Reuse (6/18/2009) |
| Designing Portability Into Silicon IP EDN Magazine (6/11/2009) |
| Tailored SoC Building Using Reconfigurable IP Blocks Design & Reuse (6/8/2009) |
| From IP Re-use to Open Innovation - A New Trend in the Industry Design & Reuse (6/4/2009) |
| H.264/AVC HDTV Motion Compensation Soft IP Design & Reuse (6/4/2009) |
| Software Interface Standard Gives New Framework Electronic Products Magazine (6/1/2009) |
| A 0.79-mm2 29-mW Real-Time Face Detection IP Core Design & Reuse (5/25/2009) |
| A Reusable Level 2 Cache Architecture Design & Reuse (5/25/2009) |
| Processor Architecture Not a Factor for Low-Power Mobile Systems EE Times Signal Processing DesignLine (4/20/2009) |
| Protecting Software IP: What Engineers Need to Know Electronic Engineering Times (EE Times) (4/20/2009) |
| Building Advanced Cortex-M3 Applications EE Times Embedded (4/8/2009) |
| Debug and Testability Features for Multi-Protocol 10G SerDes Design & Reuse (3/9/2009) |
| Analog IP Integration in SoCs: Challenges and Solutions Design & Reuse (3/3/2009) |
| How to Control Analog Output from a CPLD Using a Pulse Width Modulator EE Times Programmable Logic Designline (2/24/2009) |
| How High-Level Synthesis Can Raise the Efficiency of Design Reuse Design & Reuse (2/23/2009) |
| Leveraging Standards When Times Are Tough SOCcentral (2/16/2009) |
| Refactoring to Prepare RTL for Reuse Design & Reuse (2/16/2009) |
| Migrating From SPI 4.2 To SPI 5 IP Core: Architectural Changes and Reusability Design & Reuse (2/9/2009) |
| Trailblazing SuperSpeed USB Design and Verification Electronic Design Magazine (1/29/2009) |
| Identifying IP cores to Protect Your Investment Design & Reuse (1/26/2009) |
| Modern ADCs Improve CMOS Image Sensors EDN Magazine (1/22/2009) |
| The Value of High-Quality IP-XACT XML Design & Reuse (1/19/2009) |
| An Application Modeling and Hardware Description for Network-on-Chip Benchmarking EE Times Embedded (1/14/2009) |
| Architecting the OCP uVC Verification Component EE Times EDA Designline (1/13/2009) |
| Taking the Delay Out of Your Multicore Design'S Intra-Chip Interconnections EE Times Embedded (1/7/2009) |
| Verification IP: Solace for the Common Integration Nightmare? New Tech Press (12/24/2008) |
| Planning, Adopting and Implementing Adaptive Reuse EE Times EDA Designline (12/16/2008) |
| Planning, Adopting and Implementing Adaptive Reuse EE Times EDA Designline (11/18/2008) |
| A SystemC/TLM Based Methodology for IP Development and FPGA Prototyping EE Times EDA Designline (11/3/2008) |
| Choosing the Right Processor Candidate: the 35th Annual EDN Microprocessor Directory EDN Magazine (10/30/2008) |
| Multicore: the Future of SOCs? EDN Magazine (10/30/2008) |
| Taking the Broad View Components in Electronics (CIE) (10/1/2008) |
| How to Defend Against The Cloning of Your FPGA Designs EE Times Programmable Logic Designline (9/17/2008) |
| Building a Configurable Embedded Processor EE Times Embedded (9/9/2008) |
| Comparing an IP-Centric DDR Solution with a System-Centric DDR Solution for Improved System Performance SOCcentral (9/8/2008) |
| Debunking Multicore Design Complexities Electronic Products Magazine (9/1/2008) |
| The Five Forces Driving the Semiconductor IP Market Electronic Products Magazine (9/1/2008) |
| On-Chip Test Capabilities Solve the Analog-Test Problem for High-speed Serial Interfaces EDN Magazine (8/21/2008) |
| Build Debug and Trace Systems for Multicore SOCs Electronic Design Magazine (8/14/2008) |
| Learning Not to Fear PCI Express Compliance EE Times EDA Designline (8/12/2008) |
| Protect Your FPGA Against Piracy Electronic Design Magazine (7/10/2008) |
| RF: Will It Ever Be Plug-In IP? EDN Magazine (6/12/2008) |
| Serial ATA and the Evolution in Data Storage Technology EE Times EDA Designline (4/28/2008) |
| Integrating PCIe On-Chip Electronic Products Magazine (4/14/2008) |
| Specifying Transceivers for Serial Protocols Electronic Products Magazine (4/14/2008) |
| Interfacing High-Performance 32-bit Cores to MCU-based Memory Architectures EE Times Embedded (4/10/2008) |
| Reducing Power in Embedded Systems by Adding Hardware Accelerators EE Times Embedded (4/9/2008) |
| Implement a Complete ARV Controller in a Single SOC Electronic Design Magazine (3/27/2008) |
| Customizable Processors SOCcentral (3/11/2008) |
| Using FPGAs to Avoid Microprocessor Obsolescence EE Times Programmable Logic Designline (3/5/2008) |
| Low-Power Design for Analog/Mixed-Signal IP EE Times EDA Designline (3/4/2008) |
| Comparing IP Integration Approaches for FPGA Implementation EE Times Programmable Logic Designline (2/20/2008) |
| Multi-language Functional Verification Coverage for Multi-site Projects EE Times EDA Designline (2/18/2008) |
| Automated Formal Verification of OCP-Based IP Cores EE Times EDA Designline (1/21/2008) |
| A Chip IP Integrator for System Level Design Design & Reuse (1/14/2008) |
| USB Host IP-Core Hardware and Software Concurrent Development Design & Reuse (1/10/2008) |
| OCP VIP: A Cost-Effective and Robust Qualification Process for Multimedia and Telecom SOC Designs EE Times Embedded (1/9/2008) |
| Dealing with the Challenges of Integrating Hardware and Software Verification EE Times Embedded (1/4/2008) |
| Lower the Cost of Intelligent Power Control with FPGAs EE Times Embedded (12/15/2007) |
| Designing DDR3 SDRAM Controllers with Today's FPGAs EE Times Programmable Logic Designline (12/12/2007) |
| 4G Wireless: Evolution or Watershed in SOC Architectures? EDN Magazine (10/4/2007) |
| Regression Test for OCP SystemC Channel Models EE Times EDA Designline (9/4/2007) |
| A Bluespec Hardware Implementation of Sudoku EE Times EDA Designline (8/21/2007) |
| Verification Methodologies Keep Pace with Complex IP EE Times EDA Designline (8/14/2007) |
| Why High MHz Does Not Mean High Performance SOCcentral (5/31/2007) |
| Achieving Certified IP Quality Efficiently EE Times EDA Designline (5/29/2007) |
| Verifying Configurable Verification Interfaces Using OCP EE Times EDA Designline (5/10/2007) |
| Analog and Mixed-Signal Connectivity IP at 65nm and Below EE Times EDA Designline (5/7/2007) |
| Video Codecs in SOCs Using OCP-Based Programmable Accelerator Design Video/Imaging DesignLine (4/27/2007) |
| Rigorous Automated Verification Yields High Quality Silicon EE Times EDA Designline (4/24/2007) |
| The Growing Need for Secure Storage in Automotive Systems EE Times EDA Designline (4/6/2007) |
| Choosing to Use an SIP Rather than an SOC EDN Magazine (3/15/2007) |
| FPGA Design Issues 201 Electronic Design Magazine (3/15/2007) |
| Achieving Completeness in IP Functional Verification EE Times EDA Designline (2/12/2007) |
| Evaluating IP with the Four Cs: Compare, Consider, Collect, and Calculate EDN Magazine (2/1/2007) |
| A Logical Approach to NVM Integration in SOC Design EDN Magazine (1/18/2007) |
| Utilizing OCP to Design a High Performance Interconnect EE Times EDA Designline (1/18/2007) |
| Good Or No Good? An Insider Look at What Works for ESL Electronic Design Magazine (12/15/2006) |
| Embedded Memory Evolves EDN Magazine (12/1/2006) |
| Proprietary Architectures Defend Automotive Space EDN Magazine (12/1/2006) |
| IP Plays Cautiously in Emerging Markets EDN Magazine (11/9/2006) |
| A Layered Approach to NoC SOCcentral (10/23/2006) |
| Synchronous Interconnect is Hitting the Wall SOCcentral (10/23/2006) |
| How to Increase Confidence that Third-Party IP is Functionally Correct EE Times EDA Designline (10/1/2006) |
| Building a Total Quality Experience into Silicon IP SOCcentral (8/10/2006) |
| Verification IP Takes a Broader Role eeDesign (EE Times EDA News) (8/7/2006) |
| EDN 2006 Microprocessor Directory EDN Magazine (8/3/2006) |
| Avoiding Some Common Mistakes When Integrating USB IP Into Your SOC SOCcentral (7/3/2006) |
| Quality and Risk as a Selection Criteria for IP Using VSIA QIP 2.0 SOCcentral (7/3/2006) |
| The Love/Hate Relationship with DDR SDRAM Controllers SOCcentral (7/3/2006) |
| Evaluate IP Timing Constraints Before Use in SOC Designs SOCcentral (7/1/2006) |
| OCP "Tags" Support High-Performance SoCs eeDesign (EE Times EDA News) (5/8/2006) |
| A Hierarchy of Needs for SoC IP Reuse eeDesign (EE Times EDA News) (4/17/2006) |
| IP Integration Is Standard Fare Electronic Design Magazine (4/13/2006) |
| Choosing Hardware IP EE Times Embedded (2/1/2006) |
| Chip Assembly Challenges and Solutions eeDesign (EE Times EDA News) (1/23/2006) |
| A Practical Approach to Reusing HDL Code in FPGA Designs EE Times Programmable Logic Designline (12/28/2005) |
| Picking the Right RTOS for a Hybrid RISC/DSP Core EE Times Embedded (12/26/2005) |
| OCP-Based Memory Access Arbitration for a Digital Sampling Oscilloscope EE Times Programmable Logic Designline (12/7/2005) |
| SoC Design Success: Winning with Standards SOCcentral (11/5/2005) |
| FPGA Soft Processor Design Considerations EE Times Programmable Logic Designline (10/12/2005) |
| The Future of Configurable Microprocessing SOCcentral (9/7/2005) |
| Easing Verification Challenges for IP Reuse eeDesign (EE Times EDA News) (8/22/2005) |
| The VSIA and IP Reuse SOCcentral (8/2/2005) |
| Aggregation Drives Successful IP Reuse Chip Design Magazine (8/1/2005) |
| An IP Storm? EDN Magazine (6/23/2005) |
| IP Quality is the Key to Successful SoC Design SOCcentral (6/6/2005) |
| IP Reuse Gets a Reality Check Chip Design Magazine (6/1/2005) |
| On-Chip Nonvolatile Memory Proves Ideal for Consumer Applications Chip Design Magazine (5/1/2005) |
| SPIRIT: Structure for Packaging, Integrating, and Re-Using IP within Tool Flows Chip Design Magazine (5/1/2005) |
| Get the Lowdown On IP for Your Startup Electronic Design Magazine (4/14/2005) |
| Outpace Your Competitors With a Solid IP Plan Electronic Design Magazine (4/14/2005) |
| IP Reuse Requires a Verification Strategy eeDesign (EE Times EDA News) (2/8/2005) |
| Third-Party IP: A Shaky Foundation for SOC Design EDN Magazine (2/3/2005) |
| How Memory Architectures Affect System Performance eeDesign (EE Times EDA News) (1/31/2005) |
| "Wrap" Your Cores to Enable SoC Test eeDesign (EE Times EDA News) (11/24/2004) |
| Solve the Issues Associated with Analog-To-Digital IP Integration Electronic Design Magazine (11/15/2004) |
| Achieving Reuse with Both Modifiable IP and Configurable IP Electronic Engineering Times (EE Times) (11/8/2004) |
| Reality Check for Configurable IP Blocks Electronic Engineering Times (EE Times) (11/8/2004) |
| Relational Physical Design: No Absolutes Electronic Engineering Times (EE Times) (11/8/2004) |
| Reuse of Analog Mixed Signal IP for SoC Design Electronic Engineering Times (EE Times) (11/8/2004) |
| True Reuse Moves Well Beyond Recycling Electronic Engineering Times (EE Times) (11/8/2004) |
| Verification Issues for Reconfigurable IP Electronic Engineering Times (EE Times) (11/8/2004) |
| Debugging IP-laden Designs Chip Design Magazine (11/1/2004) |
| Logically Flashing: Mixed-Signal Verification for Flash Modules Using Co-Simulation Chip Design Magazine (11/1/2004) |
| Power Islands: The Evolving Topology of SoC Power Management Design & Reuse (11/1/2004) |
| IP Reuse Simplifies SoC Design, Verification Electronic Engineering Times (EE Times) (10/11/2004) |
| Infrastructure IPs Build ICs Out Well Electronic Engineering Times (EE Times) (10/4/2004) |
| EDA Tools for FPGAs Break Down the Complexity Gridlock EDN Magazine (9/16/2004) |
| Platform ASICs Stake the Middle Ground Electronic Engineering Times (EE Times) (9/13/2004) |
| Embedded Logic Analyzer Speeds SoPC Design Chip Design Magazine (9/1/2004) |
| Power Management IP: Coming to the Rescue for Nanometer Design Electronic Products Magazine (8/1/2004) |
| Using Formal Verification to Create Robust IP eeDesign (EE Times EDA News) (7/30/2004) |
| Best Practices for a Reusable Verification Environment Electronic Engineering Times (EE Times) (7/12/2004) |
| Delivering Verified AMBA AXI Systems-on-Chips Electronic Engineering Times (EE Times) (7/12/2004) |
| From The Outside In: Making Third-Party IP Work in Semiconductor Design Electronic Engineering Times (EE Times) (7/12/2004) |
| Platform-Based Design and Verification with Automated IP Integration Electronic Engineering Times (EE Times) (7/12/2004) |
| Specs Eye Functional Verification, Quality Electronic Engineering Times (EE Times) (7/12/2004) |
| Vendor Cooperation Necessary for Successful IP Implementation Electronic Engineering Times (EE Times) (7/12/2004) |
| Verification IP for IP Verification Electronic Engineering Times (EE Times) (7/12/2004) |
| Verifying SoCs and IP in Parallel Electronic Engineering Times (EE Times) (7/12/2004) |
| Choosing the Right Silicon Solution: When Requirements Outrun an Architecture Electronic Engineering Times (EE Times) (6/3/2004) |
| Roll Your Own Micro Chip Design Magazine (3/1/2004) |
| Analog Hard IP Made Portable Chip Design Magazine (1/1/2004) |
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