SOCcentral: Special Topics: Selecting & Integrating IP

DFM-Compliant IP: Why You Need It, How You Get It

To successfully produce designs at 65nm and below, designers must be sure all components of the design have been optimized to reduce the impact of manufacturing process variation. When some of those components are purchased from 3rd parties, designers want to be assured that those components have gone through a rigorous DFM verification process before being incorporated into the design. The process of formalizing the techniques discussed in this article has already begun. Foundries and IP vendors are stepping up to the challenge of establishing the necessary protocols and certification processes needed to create and sustain a proven, accepted standard of IP DFM certification. In addition, DFM application notes provided by the foundries are beginning to contain suggested flows and methodologies, as well as acceptance criteria for the IP designers to reference.

As we progress from 65nm to 45nm, 32nm, and beyond, and the use of IP components becomes more pervasive, chip designers must continue to have confidence that the IP they bring into their designs has met the highest DFM standards for the applicable process. The establishment of golden DFM standards and methodologies is a critical step in making that assurance possible, and allowing the continued development of complex, high-performing chips at leading process nodes.

A Processor and DSP IP Selection Checklist

SOC designs are major, high-risk projects and most consist of many IP blocks—some developed in house and some purchased. Many of the most complex blocks are processors and DSPs. With their associated software-development tools, simulation models, and EDA flow scripts, these processor IP blocks affect more than just the hardware design; their influence permeates the entire SOC design project. Consequently, processor IP can literally make or break your project. Here is a list of questions to ask yourself, your team, and any processor IP providers you contact. This list will help you to avoid unhappy IP choices and will help you get exactly what your team needs to develop successful SOC designs on time, within budget, and with minimal hassle.

The Key to Seamless and Rapid IP Integration

With the ever-growing complexity of IP and accompanying design tools, it’s imperative that SOC designers carefully weigh their options when selecting and integrating IP. For example, with the number of IP cores in embedded SOC designs growing, the bus structures to handle them are becoming more complex and time-consuming to design. As a result, multiple processors are competing for memory resources, causing memory access problems. These are just some of the challenges facing designers today when selecting and integrating IP.

It should be no surprise that the biggest contributors to SOC design cost continue to be architectural development (define the solution) and verification (knowing it is right). For many designs, there is a software part of the design extending the applications markets for an individual SOC. Many designers address this need with a platform strategy of compatible SOCs that extends the life of the design by allowing subsystems and software to be reused in future SOC designs. The software design effort exceeds that of an individual hardware platform, so reuse of proven hardware/software subsystems across several SOCs improves the cost-effectiveness of the platform. It also speeds time-to-market with subsequent SOC designs, while encouraging a growing ecosystem of application solutions for a platform. Many SOC designs have progressed to where more than 100 IP blocks are included in the SOC. In addition to reuse of simple IP cores, subsystem reuse is also a key requirement. And updated market requirements may require late changes with IP added or deleted while keeping tight schedules. As such, designers need to include IP from any source.

SoC System Management IP Virtualizes SOC System Management

Semico Research estimates that over 50 semiconductor intellectual property (IP) cores are present, on average, in SOCs being developed today, and that the number of cores will continue to increase rapidly for the foreseeable future. As a result, computer bus style SOC architectures, which have been the defacto standard for many years, are now giving way to distributed computing, multicore architectures. With all this processing now contained in the SOC, the ability to coordinate and mange all the SOC resources becomes a task which is also growing in complexity.

For many, this first shows up with coordinating access to external memory. But how do you coordinate and manage power and security among the cores? How do you coordinate error and violation recoveries? Or how do you execute boot and reset sequences? Some of these questions are being addressed today at the physical or logic design and firmware layers for specific functions, but what about the system coordination of all these? This is an architecture issue.

If we look back at the evolution of the PC architecture for direction, we discover virtualization. When the levels of complexity on the motherboard became overwhelming to manage, PCI decoupled all the functions and coordinated them through an independent system block. Now that software is becoming overwhelming, several companies are offering products that abstract and virtualize the PC software. Likewise, as the new SOC topologies are making it increasingly difficult to manage system functions, virtualization will play a role in SOCs.

Analysis shows that on the SOCs using multicore architectures today, no one IP core can easily be given enough accessibility to control the other cores without complicating the architecture. And with many software operating systems and applications present on the single SOC, synchronizing their states with their support hardware state changes is also complicated. So what role can virtualization play?

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