March 1, 2005 -- As designs get more complex, EDA-industry experts have warned, the process of verifying these designs will become more and more expensive and time consuming. In some cases, the verification process may be even more complex than the design that is being verified. In the past few years, high-performance embedded systems for control, signal-processing, and communication applications have delivered on the first part of the warning (i.e., complexity). Such system complexity has been driven by the trend to miniaturize designs and integrate multiple functional units into a single device.
To counter this increasing complexity, designers are adopting a “design-to-test” methodology. They are benefiting from the following: the bit-true simulation of Model-Based Design executable models, which identify and fix flaws during design; automatic code generation to quickly prototype designs; and the use of the original executable models to directly validate final implementations through co-simulation. This article focuses on the third benefit-namely, utilizing the original executable models for verification and validation. System-level verification through co-simulation is now a proven way to validate and verify RTL implementations. This verification and validation is possible because of the fast, bidirectional co-simulation interfaces between higher-level system-design environments and high-performance HDL simulators.
By Arun Mulpur.
This brief introduction has been excerpted from the original copyrighted article.