Page loading . . .

  
 Category: Magazine & Journal Articles Online: Article Archive 2005: Tuesday, June 18, 2013
NAND versus NOR: Which flash is Best for Booting Your Next System?  
Publication: EDN Magazine
 Printer friendly
 E-Mail Item URL

October 13, 2005 -- If you are a handset-chip architect, you have more choices than ever when it comes to picking a memory architecture for your next project. Users can go with tried-and-true methods using NOR for system booting or try their hands at designing a new architecture that boots with two of today's hybridized flash chips: Samsung's OneNAND and M-Systems' mDOC (mobile disk on chip).

The hybridized model promises to eliminate the pricey NOR device for high-end-system booting and to handle storage, too. In demand-paging architectures, it even promises to reduce the amount of RAM needed, thus reducing overall system power and cost.

But opponents say that implementing hybrid architectures is complex and error-prone. Intel, the current leader in the traditional NOR market, claims a system can make only so many "reads" from a NAND before losing data-storage integrity, which can ultimately lead to system failures, especially in demand-paging systems.

Experts say there are pluses and minuses to implementing any of the flash architectures, so users have to find the right balance of target market and user, features, unit cost, and design cost for their next designs.

By Michael Santarini, EDN Senior Editor


This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EDN Magazine website.

Keywords: EDN Magazine, flash memory,
563/16683 10/13/2005 1177 595
Designer's Mall
4th Of July countdown banner
0.171875



 Search for:
            Site       Current Category  
   Search Options


Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Reducing Power
by Raising the
Level of Abstraction


David Pursley
Director,
Product Marketing
Forte Design Systems

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Summertime and the Livin' Ain't Easy


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL?


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
184.563  0.296875