| A Practical Approach to Reusing HDL Code in FPGA Designs by Mentor Graphics Corp. in EE Times Programmable Logic Designline |
December 28, 2005 -- Despite the good efforts of the design community to espouse design-for-reuse as the Holy Grail, what many engineers – including thousands of FPGA designers like you worldwide – do in reality is recycle code. This is no dis ... read more |
| Picking the Right Computational Model by National Instruments Corp. in EE Times Embedded |
December 27, 2005 -- When design engineers step into the embedded world for the first time, they may feel like a country boy entering downtown New York City. They’re not in Kansas anymore. The embedded programming landscape can be as intimidat ... read more |
| Picking the Right RTOS for a Hybrid RISC/DSP Core by Green Hills Software, Inc. in EE Times Embedded |
December 26, 2005 -- It seems that everywhere you look today in the embedded space, there’s a new digital signal processing application. Modern video, audio, game, imaging, and communications devices use underlying algorithms that require a su ... read more |
| Delivering the Benefits of C++ Encapsulation to Your Embedded Design by Accelerated Technology in EE Times Embedded |
December 22, 2005 -- C++ can deliver real benefits specifically for the implementation of embedded software, particularly when the concept of "encapsulation of expertise" is used. By employing this technique to take advantage of the number of ... read more |
| How to Make Your Asymmetric Multiprocessor Design OS and CPU Independent by PolyCore Software, Inc. in EE Times Embedded |
December 22, 2005 -- Even as semiconductor companies tend toward multiprocessing solutions in many network, embedded consumer and mobile designs, the RTOSes and development tools are still rushing to catch up with the shift. Most multiprocessing ... read more |
| An Introduction to Symbolic Simulation by ARM in eeDesign (EE Times EDA News) |
December 19, 2005 -- Three methods for testing functional equivalence are currently available to designers — conventional simulation, cone-based equivalence checking, and symbolic simulation. Most designers are familiar with the first two, whi ... read more |
| Timing Analysis Rounds the Corner to Statistics by Electronic Design Magazine |
December 15, 2005 -- In a perfect world, fabrication of silicon ICs would be a perfectly predictable process. Not only would every chip be absolutely identical, but there would be no variations from wafer to wafer, or lot to lot. In such a par ... read more |
| An Overview of Systems Modeling Language by Artisan Software Tools in EE Times Embedded |
December 14, 2005 -- Since its inception in 1997, the Unified
Modeling Language (UML) has proved immensely popular with software engineers to
the point where it's now the only widely used visual modeling language for
software engineering ... read more |
| How to Adapt Traditional RTOSes to Symmetric Multiprocessing by Express Logic, Inc. in EE Times Embedded |
December 12, 2005 -- Mulltiprocessor (MP) and multicore System-on-Chip architectures are now beginning to be employed in a wide range of embedded consumer and communications systems. They are perceived as a way to enhance performance in applic ... read more |
| OCP-Based Memory Access Arbitration for a Digital Sampling Oscilloscope by eASIC Corp. in EE Times Programmable Logic Designline |
December 7, 2005 -- The current approach for designing an integrated circuit in the form of a System-on-Chip (SoC) is based on reusing the models for modules with a well-defined functionality. For easier interconnection, these intellectual prope ... read more |
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