| Manage Complexity in Nanometer SoC Designs by Chip Design Magazine |
June 1, 2005 -- The rapid increase in design complexity has become a serious limiting factor in nanometer system-on-a-chip (SoC) designs. This sharp increase is driven by two factors. One is the exponential rise in the number of devices integr ... read more |
| Start at the Top to Reduce Re-Spins for Analog-Digital Chips by Synopsys, Inc. in Chip Design Magazine |
June 1, 2005 -- Modern integrated-circuit design methodologies and advanced process technologies can produce complex mixed-signal devices. These devices, which are known as systems-on-a-chip (SoCs), feature a large number of digital, analog, a ... read more |
| Formal Approach Offers Verification "Salvation" by Accellera in eeDesign (EE Times EDA News) |
May 30, 2005 -- I once overheard a verification manager say, "What did I do to deserve this living hell?" Well, that is the point. It's often what we do or don't do in terms of a methodology that ultimately pulverizes our ivory tower view of t ... read more |
| Co-Design Links Chips, Boards and Packages by Electronic Engineering Times (EE Times) |
May 17, 2005 -- Chips, packages and boards have long been designed in isolation, but as silicon shrinks and complexity grows, the walls are coming down. Rising I/O counts and high-speed interfaces running up to 10 Gbits/second are prompting a ... read more |
| How FPGA Packaging Drives Signal Integrity by Xilinx, Inc. in eeDesign (EE Times EDA News) |
May 17, 2005 -- Until recently, signal integrity has been a concern relegated predominantly to multi-gigabit serial interface design. Today, it is an aspect of design that engineers building high-speed parallel interfaces like memory interface ... read more |
| Cosmic Radiation Comes to ASIC and SOC Design by EDN Magazine |
May 12, 2005 -- SEEs (single-event effects), such as soft errors, have since the early 1980s appeared in commercial electronics, but they are now becoming the dominant reliability-failure mechanism in modern CMOS technologies. Experts say that ... read more |
| Reliable Sign-off at Smaller Nodes by Cadence Design Systems, Inc. in EDN Magazine |
May 12, 2005 -- The demand for more functions and better performance continues to fuel the drive to more advanced process technologies. With each new technology generation, however, designers must deal with an increasing array of electrical an ... read more |
| A Guide to Better EMC for PC-Board Design by Zuken, Ltd. in eeDesign (EE Times EDA News) |
May 9,2005 -- Complicated RF and microwave theory is useful for designing radio equipment, but digital designers aim to avoid turning circuits into radios without the benefit of an RF engineering degree. In digital design, the number of possib ... read more |
| SoC Processing Options by Texas Instruments, Inc. (TI) in Electronic Engineering Times (EE Times) |
May 2, 2005 -- Systems-on-chip with multiple processing elements are an important part of the design landscape, especially for portable systems that require the high level of integration and the mixed data and signal processing that SoC device ... read more |
| The "Why" and "What" of Algorithmic Synthesis by Mentor Graphics Corp. in eeDesign (EE Times EDA News) |
May 2, 2005 -- Algorithmic synthesis helps hardware designers build and verify hardware more efficiently, giving them better control over optimization of their design architecture. The starting point of this flow is a subset of pure C++ that i ... read more |
|
