| Best Practices for Structured-ASIC Design by ChipX Corp. in Electronic Engineering Times (EE Times) |
October 17, 2005 -- Given the increasing nonrecurring engineering charges and long design schedules associated with deep-submicron standard-cell ASICs, the use of structured ASICs for custom IC design is an increasingly attractive option. Stru ... read more |
| Packaging Rides the Z Axis Into the Third Dimension by Electronic Design Magazine |
October 13, 2005 -- The push for 3D packaging of semiconductor ICs directly results from market demands for smaller and lower-profile, lighter, and lower-cost packaged ICs that consume less power. With such market forces at play, package desig ... read more |
| The Secrets of Successful Communications Using LVDS by Texas Instruments, Inc. (TI) in EDN Magazine |
October 13, 2005 -- Many choices now exist for LVDS (low-voltage differential-signaling) devices. Versions of these devices often coexist in the same system, which creates interoperability concerns. Among the available and practical versions, ... read more |
| NAND versus NOR: Which flash is Best for Booting Your Next System? by EDN Magazine |
October 13, 2005 -- If you are a handset-chip architect, you have more choices than ever when it comes to picking a memory architecture for your next project. Users can go with tried-and-true methods using NOR for system booting or try their h ... read more |
| FPGA Soft Processor Design Considerations by EE Times Programmable Logic Designline |
October 12, 2005 -- All design teams struggle under the pressure to shorten product development cycles while taxed with incorporating features superior to existing competitive products. This ever-shrinking development cycle also drives higher le ... read more |
| Designing ASICs for Supersystems by Hewlett-Packard in Electronic Engineering Times (EE Times) |
October 10, 2005 -- During the past five years, ASIC system-on-chip design has taken on a new dimension — namely, that of ASIC SSOC (supersystem-on-chip) design. SSOCs have multiple processor cores and buses, and more than 10 million logic gat ... read more |
| Static and Dynamic Modeling for High-Density Memories by HCL Technologies, Ltd. in eeDesign (EE Times EDA News) |
October 10, 2005 -- As designs increase in complexity, the density of memories that they connect to has also increased. It is not uncommon to see gigabyte memories. Having large memories comes with its own set of challenges during the verifica ... read more |
| Verification Moves to a Higher Level by Brian Bailey in eeDesign (EE Times EDA News) |
October 3, 2005 -- Significant advances in verification productivity have occurred recently, particularly in testbench development, making it quicker and easier to develop new tests. These advances also reduce the maintenance time for existing ... read more |
| Flexible Silicon: GUI-Programmable Audio Processors by EDN Magazine |
September 29, 2005 -- A simple categorization assigns most
signal-processing blocks to one of two groups. On the one hand are generic
functions, such as op amps and ADCs, which perform one task and may serve in
many disparate application ... read more |
| Architectural-Design Considerations for Implementing Hardware Acceleration by QuickLogic Corp. in EDN Magazine |
September 29. 2005 -- Across a range of embedded-system applications, the combination of data-processing and system throughput requirements is increasing to the point at which implementing algorithms purely in software on a single high-powered ... read more |
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