| An Introduction to PLM for EDA by MatrixOne, Inc. in eeDesign (EE Times EDA News) |
December 28, 2004 -- Business pressures on semiconductor companies are relentless. Meanwhile, Moore's Law marches on. Circuit densities are ten times what they were just three years ago. Furthermore, a growing number of designs have moved to highly com ... read more |
| Wireless Tries New Way to Slim Down by Tessera, Inc. in Electronic Engineering Times (EE Times) |
December 20, 2004 -- Over the past two decades, the cellular phone industry has turned largely to advancements in electronics packaging to meet its need for small, highly reliable electronics. These demands are growing more acute as the line b ... read more |
| SoC Package Design Takes "Bottom-Up" Tack by LSI Corp. in Electronic Engineering Times (EE Times) |
December 20, 2004 -- As system-on-chip designs migrate to nanometer silicon, packaging technology is challenged to keep pace with the integration and performance capabilities offered. Nowhere is this more so than in communication and networkin ... read more |
| High-Speed Chips Advance Signal Integrity by Integrated Device Technology, Inc. (IDT) in Electronic Engineering Times (EE Times) |
December 20, 2004 -- Today's sophisticated communication system designs use large, high-power, high-pin-count BGA devices, running parallel source-synchronous buses at speeds exceeding 500 MHz. Devices can have well over 1,000 contacts and can ... read more |
| SiPs Offer Alternative to SoCs for Comms by Philips Semiconductors NV in Electronic Engineering Times (EE Times) |
December 20, 2004 -- Several companies, notably fabless ones, are promoting all-CMOS system-on-chip (SoC) solutions to RF applications. While certain applications, notably lower-performance ones, can now utilize SoC solutions, these are unlike ... read more |
| LTCC Packaging for Wireless UWB Applications by Staccato Communications, Inc. in Electronic Engineering Times (EE Times) |
December 20, 2004 -- As the sophistication of wireless technologies evolves and operating bandwidths and frequencies continue to climb, the need for advanced packaging solutions become more evident. High-frequency loss, such parasitics as bond ... read more |
| Compiling Software to Gates by in EE Times Embedded |
December 20, 2004 -- Crisis, what crisis? A hard question, not because there is no crisis, but because there are so many affecting the semiconductor industry. The crises include the rising cost to create a state-of-art chip, the time it takes ... read more |
| Back to the Language Roots by ASIC Group (The) in EE Times Embedded |
December 20, 2004 -- Traditional hardware-description languages have specific features that make them superior to software programming languages; although SystemC has its place in the hardware-design process, it still can't compete with Verilo ... read more |
| Spinning Spheres Test Relativity's Subtlety by EDN Magazine |
December 17, 2004 -- On April 20, 2004, a Boeing Delta II rocket launched from Vandenberg Air Force Base carried Gravity Probe B into orbit and so initiated the next step in a 40-year quest to verify a corollary of the General Theory of Relativi ... read more |
| Mixed-Level Modeling Allows IC Virtual Prototypes by Synopsys, Inc. in eeDesign (EE Times EDA News) |
December 16, 2004 -- The continuing advancements in semiconductor technology have led to production flows for 130nm, 90nm and below, enabling 40 million-plus gate chips to be reliably manufactured. This article explores the methodologies and too ... read more |
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