March 3, 2003 -- "In the IC design flow, design-for-test is often an afterthought. First, the design is coded, then simulated, then synthesized, and only after all that - usually months into the design cycle - it's handed over to a test team to ensure the design is testable. And often it isn't.
"Most RTL designers have never had to insert test vectors into their own designs. They're not held accountable for the testability of their designs. They don't even understand that there is a lot they can do to make their designs more testable.
"Why should RTL designers care? If RTL designers don't properly apply testability rules at the initial design stage, the design can have poor test coverage or even be untestable until extensive changes are made. Besides saving valuable test engineering time, proper design techniques result in code that is much more reusable. Testability issues create requirements to make changes at the gate level that are rarely reflected back into the RTL code."
By Ralph Marlett. (Marlett is Product Director, Atrenta, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Electronic Engineering Times (EE Times) website.
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