June 9, 2003 -- With today's increasingly large and complex digital IC and system-on-chip (SoC) designs, design power closure and circuit power integrity are starting to become one of the main engineering challenges, thereby impacting the device's total time-to-market.
The shear amount of power consumed by some devices can cause significant design problems. For example, a recently announced CPU consumes 100 amps at 1.3 volts, which equates to 130 Watts! This class of device requires expensive packaging and heat sinks. The heat gradient across the chip can cause mechanical stress leading to early breakdown, and the act of physically delivering all of this power into the chip is non-trivial. Thus, even in the case of devices intended for use in non-portable equipment where ample power is readily available, power-aware designs can offer competitive advantages with respect to such considerations as the size and cost of the power supply and cooling systems.
By Sameer Patel. (Patel is director of product marketing at Magma Design Automation.)
This brief introduction has been excerpted from the original copyrighted article.