April 25, 2007 -- Sonics, Inc. and Denali Software, Inc. are collaborating to address memory bandwidth optimization through the pairing of Sonics SMART Interconnect solutions and Denali Databahn DDR memory controllers. Companies using both Sonics SMART Interconnect solutions and Denali's Databahn are now able to quickly and efficiently deploy memory subsystems and on-chip interconnects to deliver optimal memory bandwidth utilization for multi-core SOC designs.
"The trend toward multi-core designs adds significant complexity to the memory subsystem and interconnect design for today's SOCs," said Drew Wingard, Chief Technology Officer, Sonics, Inc. "The SOC designer must ensure that all the processing and input/output elements in the system are served with the required levels of memory bandwidth with acceptable latency while ensuring high efficiency access to external DRAM. By teaming with Denali, we've ensured the on-chip interconnect and memory controller IP interoperate so that our mutual customers can offload much of the time and risk associated with developing these memory subsystems."
This collaboration addresses the problems associated with increasing external memory bandwidth requirements and a transition from single processor architectures to multicore architectures. As new SOC designs continue to absorb more system functionality, the need for intelligent management of memory resources become even more critical.
"Developers of consumer electronics are challenged to design complex, multi-core SOCs," said Brian Gardner, Vice President of IP Products at Denali. "These customers need configurable, proven solutions that can be rapidly deployed for memory subsystems and SoC interconnects. With Sonics, we are able to combine the two best-in-class solutions and meet these demanding needs."
Go to the Sonics, Inc. website to find additional information.