| Centralized Storage Caching Fixes the EDA Compute Bottleneck by EE Times EDA Designline |
December 31, 2006 -- EDA users drive powerful requirements for the underlying computer and data storage infrastructure. In particular, many aspects of the EDA process such as regression testing and correction processing engines like Synopsys' Pr ... read more |
| Practical Applications of Statistical Static Timing Analysis by Cadence Design Systems, Inc. in EE Times EDA Designline |
December 18, 2006 -- As the electronic design industry continues to push the limits of Moore's Law, a paradigm shift in timing analysis must be considered. The major reason for this is overly pessimistic timing analysis, which threatens to negat ... read more |
| Quickly Find Elusive Signal-Integrity Problems in High-Speed Designs by Agilent Technologies, Inc. in Electronic Design Magazine |
December 15, 2006 -- Traditional approaches to finding signal-integrity issues in high-speed electronic designs involve using hardware triggering to isolate the event and/or deep memory time acquisitions to capture the event and then find it lat ... read more |
| Good Or No Good? An Insider Look at What Works for ESL by Electronic Design Magazine |
December 15, 2006 -- ESL design flows are for real. They're in use
right now at some of the world's largest systems houses, and with those flows,
chips are being taped out and put into production. So obviously, ESL flows can
be made to wor ... read more |
| PSL Verification Package for the Open Core Protocol by EE Times EDA Designline |
December 14, 2006Nokia utilizes the Open Core Protocol (OCP) as a standard interconnection architecture for its systems. So far there has not been a unified verification methodology for interconnections available. As a consequence, there was an ... read more |
| Floating-point Arithmetic on FPGAs by Xilinx, Inc. in EE Times Signal Processing DesignLine |
December 13, 2006 -- You would think that integers work fine, but that is not always the case. The problem with integers is the lack of dynamic range and rounding errors. This article explains the basics of floating-point arithmetic, how floatin ... read more |
| Overcoming High-Volume IC Design Challenges to Maximize Profits by Pulsic, Ltd. in EE Times EDA Designline |
December 11, 2006 -- Although competitive edge is usually derived from time-to-market, more importantly it is derived from time-to-yield advantages. As geometries shrink, design challenges require innovative solutions to deliver maximum profit. ... read more |
| Globalization in an Analog/Mixed-Signal World by Tanner EDA in EE Times EDA Designline |
December 7, 2006 -- In the modern era of electronics, designers, manufacturers, distributors, and customers all do business in a global market. The truth is undeniable—globalization is here to stay, and companies that want to succeed must deal w ... read more |
| Graphical Tools for Rapid Sesign, Prototyping, and Deployment by National Instruments Corp. in EE Times Signal Processing DesignLine |
December 6, 2006 -- You can find embedded processors in objects such as shoes, phones, toasters, and automobiles, requiring an ever-growing range of engineers to design embedded systems. With so many engineers needing embedded technologies and s ... read more |
| Enterprise System Level (ESL) Verification - Part 2 by Cadence Design Systems, Inc. in EE Times EDA Designline |
December 4, 2006 -- In the first part of this two part series we spent a significant portion of the article addressing the anticipation, or as some would say "state of confusion" in ESL as it stands t ... read more |
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