December 18, 2006 -- As the electronic design industry continues to push the limits of Moore's Law, a paradigm shift in timing analysis must be considered. The major reason for this is overly pessimistic timing analysis, which threatens to negate many of the benefits that smaller process geometries offer. Static timing analysis (STA) cannot properly account for the variability inherent in semiconductor processes, making exaggerated pessimism a necessary evil. Process variation " which at 90nm and above had a manageable impact on delay " has a much more dramatic effect as process geometries shrink. The reason this occurs is that process control becomes more difficult at smaller process nodes. Even if the amount of variation remained the same as in previous generations, it will account for a greater percentage of process geometries as they get smaller.
Statistics is emerging as the most likely vehicle to carry the industry forward into the future of timing analysis. Using a statistical approach it will be possible to break beyond the barriers of case analysis and begin to holistically model the factors affecting process variation in a single analysis run. This will not only obviate the need for corners but remove much of their inherent pessimism. The results will be in the form of a probability density function (PDF) " for instance a normal Gaussian distribution " which will indicate the probability of failure for a given timing slack, rather than the traditional slack number. This enables designers and management to evaluate parametric yield for a desired performance target " a key facet of Statistical Static Timing Analysis (SSTA).
By Parveen Khurana and Michael Jacobs. (Khurana is technical lead of Tthe timing group at Cadence India, Jacobs has served in the capacity of design services, technical field applications, and product marketing supporting digital verification and RTL to GDSII solutions with Cadence Design Systems, Inc.)
This brief introduction has been excerpted from the original copyrighted article.