January 7, 2008 -- Xilinx, Inc. has introduced the Xilinx Automotive (XA) Spartan-3A and Spartan-3A DSP FPGAs, significantly expanding its portfolio of low-cost automotive-qualified devices. These new offerings bring domain-optimized solutions for high I/O-logic ratio and high-bandwidth digital signal processing (DSP) with low power consumption and advanced design security to the development of infotainment, hybrid cluster, and driver assistance systems.

XA Spartan-3A FPGAs offer the highest number of I/O per logic cell with broad connectivity support, providing flexibility and scalability for I/O-intensive display and LED backlight applications. XA Spartan-3A DSP devices add more logic, memory, and XtremeDSP slices, providing more raw DSP throughput than any other low-cost PLD device. The addition of these two families to the XA portfolio delivers FPGA-based solutions optimized for TFT displays, image and video processing, and in-vehicle networking in automotive applications.

XA Spartan-3A FPGAs target hybrid cluster systems

Next-generation instrument clusters (dashboards) will be a mix of analog and digital functionality. These hybrid clusters require high I/O count in order to control analog gauges and LED lighting, as well as advanced I/O capabilities such as LVDS and RSDS to intelligently control displays. For example, LED backlighting, where each LED in the cluster must be adjusted for color and brightness, was previously managed using a CPLD along side a microcontroller. Now, this all can be integrated on-board in XA Spartan-3A devices with the embedded Xilinx 32-bit MicroBlaze soft microprocessor.

XA Spartan-3A devices are I/O-optimized for the lowest cost per I/O, with up to 1.4 million system gates and 502 I/Os. These FPGAs are compliant with 26 popular single-ended and differential signaling standards, and also support market-specific networking standards, such as CAN, MOST and FlexRay, for which Xilinx has full solutions available. These devices use source-synchronous interfacing technology cost-optimized to ensure optimal design margins. They also introduce an array of features that include dual-power management (suspend and hibernate modes); device configuration capabilities; reduction in the number of power rails (power lines going into the device) from three to two; and permanent DeviceDNA serial numbering to safeguard hardware and software intellectual property (IP).

XA Spartan-3A FPGAs target DSP needs

XA Spartan-3A DSP devices deliver over 30GMACS and 2200Gbps memory bandwidth, closing the bandwidth gap automotive designers face with current serial DSP designs. The cost-optimized XtremeDSP DSP48A slice lets designers implement many independent arithmetic functions. Multiple slices can be connected together without the use of general logic fabric, reducing power consumption while delivering very high performance and efficient silicon utilization. These slices combined with hard-coded DSP pre-adder and multiply accumulate (MAC) blocks provide more than enough processing capacity to execute complex image algorithms much faster than any serial DSP on the automotive market today. In addition, the XA Spartan-3A DSP family provides up to 53,712 logic cells, 2268kbits of performance-enhanced Block RAM, and 373kbits of distributed RAM that collectively can be configured to optimize for a broad range of signal processing requirements.

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