January 14, 2008 -- Lattice Semiconductor Corp. today announced its LatticeECP2 and LatticeECP2M FPGA interface reference design supporting the Texas Instruments’ ADS6000 family of analog-to-digital converters (ADCs). LatticeECP2/M FPGAs provide a high-speed glueless interface capable of acquiring 14-bit ADC data at rates up to 120MSPS from the two to four serial channels found in ADS6000 ADC family devices.

Systems migrating to higher sample rate/ resolution ADCs often require an FPGA with an interface speed of approximately 800Mbps to bridge existing hardware and the newer interface provided by the higher speed ADC. Previously, only more expensive, high-end FPGAs could satisfy this requirement. Now, the LatticeECP2/M FPGA family is able to provide these bridge functions in an optimally sized FPGA at a significantly lower cost. With the LatticeECP2/M FPGA devices, designers can focus on processing the ADC data within the FPGA and routing it to other parts of their system without having to worry about the timing details of high-speed ADC interfaces.

To facilitate design verification, the default configuration of the reference design utilizes a new hardware interface card developed by Lattice to work with existing TI and Lattice evaluation boards. This complete hardware/ software package gives designers a working model from which they can quickly create their own custom solutions.

"The combination of the LatticeECP2/M FPGA reference design and TI’s ADS6000 solutions boards provides a quick and cost-effective evaluation platform for receiver solutions targeting advanced communications, imaging, test and measurement and video applications," said Heinz-Peter Beckemeyer, Manager of TI’s High Speed Data Converter product line. "The latest offering enables users to reach the market fast with a cost-optimized FPGA and multi-channel ADC solution that combines exceptional speed, performance, size and power."

The TI ADC interface card, available immediately from the Lattice website, enables the interfacing of the ADS6425EVM evaluation board directly with the LatticeECP2 advanced evaluation board. The reference design uses about 5% of the FPGA logic to transfer the ADC codes on the serial source synchronous bus to its embedded block RAM memory.

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