January 21, 2008 -- Magma Design Automation, Inc., Mentor Graphics Corp., and Synopsys, Inc. announced that the three companies are now delivering low-power EDA tools based on the Accellera-developed Unified Power Format standard, UPF 1.0. This includes a broad range of implementation and verification products from the three companies. This new UPF product support further enhances key low-power capabilities in the companies' tools while expanding industry interoperability, especially when compared to other available options.

The UPF standard enables end users to create a consistent, succinct, unified description of the low power design intent for use by EDA tools offering advanced features for design and verification of today's low power integrated circuits. This benefits designers in two key ways. First, UPF supports integrated low power design flows from RTL to silicon, enabling consistent low-power design intent to be applied and used throughout the flow. Second, the UPF standard enables interoperability, so tools from over two-thirds of the EDA marketplace can be used together utilizing the same low power methodology and design specifications.

"Power management is a key challenge for all leading-edge chip designs, whether they are targeted for wireless consumer devices or large compute servers plugged into the wall," said Kam Kittrell, General Manager of Magma's Design Implementation Business Unit. "It's not sufficient for each EDA tool to handle these challenges individually. All the tools that make up the design environment, including implementation, verification and analysis, must do so in a consistent manner. UPF enables tool interoperability, allowing effective specification and power management across the entire design tool spectrum, and brings tremendous value to the design community."

"UPF came about from the low-power design industry's challenge to Accellera to define an open, inclusive low-power design format. Mentor Graphics and the EDA industry have embraced the UPF standard and are now delivering on the promise of design tool interoperability in low-power design flows and the portability of low-power design data," said Stephen Bailey, Functional Verification Product Marketing Manager at Mentor Graphics. "The level of interest in UPF-based solutions portend a bright future for this new standard."

"The UPF Standard represents a win/ win/ win for industry interoperability and cooperation," said Rich Goldman, Vice President of Strategic Market Development at Synopsys. "Design teams win from better low power flows and greater tool interoperability, EDA vendors win from a consistent Accellera/IEEE standard and the world wins from chips that consume far less energy. Through low-power design, electrical engineers will be a major contributing factor in helping the world resolve its climate change challenges, and the EDA industry will help them get there."

Availability